A memory evaluation method includes determining a health degree evaluation model indicating a relationship in which a health degree of a memory changes with at least one health degree influencing factor of the memory; obtaining at least one running parameter value corresponding to each of the at least one health degree influencing factor; separately matching the at least one running parameter value corresponding to each health degree influencing factor to the health degree evaluation model, to obtain the health degree of the memory; and outputting health degree indication information indicating whether the memory needs to be replaced.

A method for graphics processor clock scaling comprises the following steps. A percentage of idle-time is calculated, based upon an elapsed idle-time and an elapsed active time. A graphics processor clock rate is reduced if the percentage of idle time is higher than a high limit threshold. The graphics processor clock rate is increased if the percentage of idle time is lower than a low limit threshold.

A method includes reading first and second timer count values from a timer. The first timer count value is associated with a first time point, and the second timer count value is associated with a second time point. Also, the method includes calculating a difference between the first and the second timer count values, and determining whether the difference is within a range. The range is based on a desired executing frequency to perform a computing task, a variation of the desired executing frequency, and a timer frequency. Further, based on the difference not being within the range, the method includes setting an error flag value to be true and incrementing an error count value.

Described herein are systems and techniques for determining when excessive I/O response times are not the fault of a storage port, but rather are caused by other factors or components on a storage network, for example, over-utilization of a host port. For one or more host ports and/or storage ports, a payload idle time (PIT) may be determined for each I/O operation, the PIT being the amount of time during which a storage port is waiting for a host port to be ready to send or receive data of the respective I/O operation. It may be determined whether one or more of the PITs includes an excessive idle time (EIT), where the EIT may be an amount of the PIT that is more than a predefined acceptable amount of time. The cause of the EIT may be determined.

The detection of utilized virtual machines through usage pattern analysis is described. In one example, a computing device can collect utilization metrics from a virtual machine over time. The utilization metrics can be related to one or more processing usage, disk usage, network usage, and memory usage metrics, among others. The utilization metrics can be used to determine a number of clusters, and the clusters can be used to organize the utilization metrics into groups. Depending upon the number or overall percentage of the utilization metrics assigned to individual ones of the plurality of clusters, it is possible to determine whether or not the virtual machine is a utilized or an idle virtual machine. Once identified, utilized virtual machines can be migrated in some cases. Idle virtual machines can be shut down to conserve processing resources and costs in some cases.

Technologies for providing predictive thermal management include a compute device. The compute device includes a compute engine and an execution assistant device to assist the compute engine in the execution of a workload. The compute engine is configured to obtain a profile that relates a utilization factor indicative of a present amount of activity of the execution assistant device to a predicted temperature of the execution assistant device, determine, as the execution assistant device assists in the execution of the workload, a value of the utilization factor of the execution assistant device, determine, as a function of the determined value of the utilization factor and the obtained profile, the predicted temperature of the execution assistant device, determine whether the predicted temperature satisfies a predefined threshold temperature, and adjust, in response to a determination that the predicted temperature satisfies the predefined threshold temperature, an operation of the compute device to reduce the predicted temperature. Other embodiments are also described and claimed.

This application relates to a method for optimizing algorithm performance using precision scaling, wherein the method according to an embodiment of present invention comprises obtaining a number of iterations of a unit operation according to precisions of the algorithm including the unit operation that is repeatedly performed, wherein the precisions include a first precision and a second precision, and the number of iterations include a first number of iterations corresponding to the first precision and a second number of iterations corresponding to the second precision; inspecting available precisions of a device on which the algorithm is to be executed, wherein the available precisions include a first available precision corresponding to the first precision and a second available precision corresponding to the second precision; determining an optimal precision by repeatedly performing the unit operation corresponding to an initial operation of the algorithm using the inspected available precision; and repeatedly performing the unit operation corresponding to a remaining operation of the algorithm with the optimal precision.

A performance influence involved in system transition is evaluated in consideration of a timer set for each processing section. An evaluation device 1 includes a storage device 10 that stores processing section data 11 in which a maximum time from start to expiration of a timer is associated with an identifier of a processing section in which the timer is set, an average waiting time calculating unit 21 that calculates an average waiting time of a service request based on a turnaround time necessary for processing in the accumulation device 4 for each processing section, and as evaluation unit 22 that evaluates that data used in the processing section is not separable to the accumulation device 4 when the maximum time of the timer set in the processing section is less than the sum of the average waiting time and a traffic amount per unit time.

In some examples, a system receives data from peripheral devices connected to respective point-of-sale (POS) base terminals, the data captured using agents executing in the POS base terminals during periods of reduced activity of the POS base terminals. Based on processing the received data, the system determines linkage of peripheral devices to the POS base terminals, and determines, for a first POS base terminal, swapping of a first peripheral device with a second peripheral device. The system generates an output indicating that the first peripheral device has been swapped with the second peripheral device, and identifies an issue associated with a POS base terminal or a peripheral device, and trigger a remediation action to address the issue.

A processing system includes a memory controller that preemptively exits a dynamic random access (DRAM) integrated circuit rank from a low power mode such as power down mode based on a predicted time when the memory controller will receive a request to access the DRAM rank. The memory controller tracks how long after a DRAM rank enters the low power mode before a request to access the DRAM rank is received by the memory controller. Based on a history of the timing of access requests, the memory controller predicts for each DRAM rank a predicted time reflecting how long after entering low power mode a request to access each DRAM rank is expected to be received. The memory controller speculatively exits the DRAM rank from the low power mode based on the predicted time and prior to receiving a request to access the DRAM IC rank.