During execution of garbage collection, an application receives a first request to overwrite a reference field of an object, the object comprising a first reference and the first request comprising a memory address at which the reference field is stored, and a second reference to be written to the reference field. Responsive to receiving the first request, the system determines a current remembered set phase, and loads the first reference. The application determines that remembered set metadata of the first reference does not match the current remembered set phase. Responsive to that determination, the application adds an entry to a remembered set data structure, modifies the second reference to include the current remembered set phase as the remembered set metadata, and stores the modified second reference to the reference field. In subsequent writes to the reference field, the application refrains from adding to the remembered set data structure.

A storage device for performing a garbage collection operation using a partial block erase operation includes: a memory device including a plurality of main blocks each including a plurality of sub-blocks; and a memory controller configured to perform a garbage collection operation for securing free blocks in which no data is stored, among the main blocks, wherein the memory controller includes a write handler configured to erase at least a portion of a target block, among the main blocks, according to whether an amount of valid data in at least one victim block exceeds a storage capacity of one main block.

Methods, microprocessors, and systems are provided for implementing an artificial neural network. Data buffers in virtual memory are coupled to respective processing layers in the artificial neural network. An ordered visiting sequence of layers of the artificial neural network is obtained. A virtual memory allocation schedule is produced as a function of the ordered visiting sequence of layers of the artificial neural network, the schedule including a set of instructions for memory allocation and deallocation operations applicable to the data buffers. A physical memory configuration dataset is computed as a function of the virtual memory allocation schedule for the artificial neural network, the dataset including sizes and addresses of physical memory locations for the artificial neural network.

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

An arena-based memory management system is disclosed. In response to a call to reclaim memory storing a group of objects allocated in an arena, an object not in use of the group of objects allocated in the arena is collected. A live object of the plurality of objects is copied from the arena to a heap.

Systems and methods are described for providing rapid access to data sets used by serverless function executions. Rather than pre-loading an entire data set into an environment of a serverless function, which might incur large latencies, the environment is provided with a local access view of the data set, such as in the form of a read-only mount point. As blocks within the data set are requested, a local process can translate the requests into requests for corresponding network objects. The network objects are then retrieved, and the relevant portion of the object is made available to the environment. Network objects may be shared among multiple data sets, so a host device may include a cache enabling an object retrieved for a first environment to also be used to service requests from a second environment.

Managing secondary objects efficiently increases garbage collection concurrency and reduces object storage requirements. Aliveness marking of secondary objects is integrated with aliveness marking of referenced objects. Allocation of reference-sized secondary object identifier fields in objects which are not primary objects is avoided; a dedicated bit specifies primary objects, together with an object relationship table. A primary object is one with at least one secondary object which is deemed alive by garbage collection if the primary object is alive, without being a referenced object of the primary object. Any referenced objects of the alive primary object will also still be deemed alive. Code paths for marking referenced objects can be shared to allow more efficient secondary object marking. Primary-secondary object relationships may be represented in dependent handles, and may be specified in a hash table or other data structure.

Systems and methods data storage device performance prediction based on garbage collection resources are described. The data storage device may process host storage operations and determine a valid fragment count parameter for a current or future data block. Based on the valid fragment count parameter a predicted performance value for host storage operations is determined and the host device is notified of the predicted performance value.

According to one embodiment, a memory system manages a plurality of management tables corresponding to a plurality of first blocks in a nonvolatile memory. Each management table includes a plurality of reference counts corresponding to a plurality of data in a corresponding first block. The memory system copies a set of data included in a copy-source block for garbage collection and corresponding respectively to reference counts belonging to a first reference count range to a first copy-destination block, and copies a set of data included in the copy-source block and corresponding respectively to reference counts belonging to a second reference count range having a lower limit higher than an upper limit of the first reference count range to a second copy-destination block.

A data storage device can be arranged with a semiconductor memory having a plurality of erasure blocks accessed by a controller to store data. An access count for each respective erasure block can be generated to allow a wear range for the semiconductor memory to be computed based on the respective access counts with the controller. A performance impact of the wear range is evaluated with the controller in order to intelligently alter a deterministic window of a first erasure block of the plurality of erasure blocks in response to the performance impact.