G06F12/0661

Method for assigning addresses to nodes of a bus system, and installation
09965427 · 2018-05-08 · ·

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

REVOCATION AND UPDATING OF COMPROMISED ROOT OF TRUST (ROT)

Disclosed are implementation for revoking and updating a compromised root-of-trust (ROT), including a method comprising determining whether a current validation value, representative of an expected value resulting from application of a validation function to a current certificate, is to be replaced, with the current validation value being stored in a write-restricted non-volatile memory unit of the device. The method also comprises determining at boot time whether a physical presence indicator, configured to be non-actuatable from non-proximate locations, is set to a value indicating that an actuation mechanism (for actuating the physical presence indicator so as to cause content change for the write-restricted memory), has established physical presence with the device, and providing a new validation value in response to determining that the current validation value is to be replaced and that the physical presence indicator indicates that physical presence has been established.

Dynamic address change optimizations

Component circuitry for a replaceable printer component, including a dynamic address generator which selectively generates component addresses, wherein substantially immediately following an event, the component circuitry performs in succession a plurality of sets of operations, each set of operations including receiving an address change request from a master and generating a new component address by the dynamic address generator in response, a last one of the new component addresses generated being available as the component address for the component circuitry in one or more subsequent communications with the master.

SELECTIVELY-ACTIVATED TERMINATION CIRCUITRY, AND ASSOCIATED SYSTEMS, METHODS, AND DEVICES
20250045203 · 2025-02-06 ·

Memory systems are disclosed. A memory system may include a plurality of memory devices and a controller in communication with the plurality of memory devices. The controller may be configured to load respective select information to at least some memory devices of the plurality of memory devices. Each memory device of the at least some memory devices may be configured to store its respective select information. Further, each memory device of the at least some memory devices may be configured to adjust, based on the stored select information and in response to receipt of a signal at the memory device, an impedance characteristic of the memory device during at least a portion of a memory device operation of another memory device of the plurality of memory devices. Associated methods and devices are also disclosed.

METHOD FOR ASSIGNING ADDRESSES TO NODES OF A BUS SYSTEM, AND INSTALLATION
20170185553 · 2017-06-29 ·

A method for assigning addresses to nodes of a bus system, and installation, bus nodes being furnished with an identical delivery address, where (i) an assigning entity, particularly a central computer, start-up computer or bus node sends information to the delivery address via the bus system, (ii) the information includes a first address, (iii) an action is performed whose effect is detected by a first bus node, (iv) the first bus node accepts the first address, (v) the first bus node sends a response to the assigning entity, and (vi) steps (i) through (v) are repeated, each time with a further address for a further bus node.

Apparatus having selectively-activated termination circuitry
12235760 · 2025-02-25 · ·

Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.

Virtual grouping of memory

The present disclosure includes identifying, in a memory system, a capacity for each of a plurality of memory modules for a first memory channel having a first amount of memory and a second memory channel having a second amount of memory; determining a memory segment size from the capacities of the memory modules; identifying a first memory segment of the memory segment size for the first memory channel and a second memory segment of the memory segment size for the second memory channel; and creating a virtual group that includes the first memory segment and the second memory segment and that uses less than the entire first amount of memory from the first memory channel.

LINE TERMINATION METHODS
20170068617 · 2017-03-09 · ·

Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.

System and method for controlling multiple serial control devices in an emergency vehicle

A system, method and storage medium for configuring and operating a plurality of serial devices in an emergency response vehicle. The system may include a plurality of peripheral devices, each configured to receive and store an address, a controller configured to transmit addressable commands to each of the devices, at least two of the devices having a first device type wherein the addresses of each of the devices are selectable by a user. The method may include selecting a plurality of peripheral devices, each configured to receive and store an address, with at least two of the devices have a same device type, connecting each of the devices to a computer executing configuration software, detecting each of the devices, receiving an address for at least one of the devices, and storing the address in a storage medium.

Data migration method and apparatus

The present invention provides a data migration method and apparatus, where the method includes: after a second control board is inserted into a second control board slot, receiving, by a first control board, type information from the second control board, and determining whether the type information of the second control board and type information of the first control board are the same; and when determining that the type information of the second control board and the type information of the first control board are different, sending, by the first control board, configuration data stored by the first control board itself to the second control board, so that the second control board utilizes the configuration data to perform a configuration.