A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.

The present technique provides an apparatus and method for caching data. The apparatus has a cache storage to cache data associated with memory addresses, a first interface to receive access requests, where each access request is a request to access data at a memory address indicated by that access request, and a second interface to couple to a memory controller used to control access to memory. Further, cache control circuitry is used to control allocation of data into the cache storage in accordance with a power consumption based allocation policy that seeks to select which data is cached in the cache storage with the aim of conserving power associated with accesses to the memory via the second interface. A given access request considered by the cache control circuitry is provided with associated cache hint information providing one or more usage indications for given data at the memory address indicated by that given access request, and the cache control circuitry is arranged to reference the associated cache hint information when applying the power consumption based allocation policy to determine whether to cache the given data in the cache storage.

A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

A server includes a data cache for storing data objects requested by users logged in under different user roles. Different user roles may have different permissions to access individual fields within a data object. When a cache miss occurs, the cache may begin loading portions of a requested data object from various data sources. Instead of waiting for the entire object to load to change the object state to “valid,” the cache may incrementally update the state through various levels of validity based on the user role of the request. When a portion of the data object used by a low-level user role is received, the object state can be upgraded to be valid for that user role while data for higher-level user roles continues to load. The portion of the data object can then be sent to the low-level user roles without waiting for the rest of the data object to load.

A server includes a data cache for storing data objects requested by users logged in under different user roles. Different user roles may have different permissions to access individual fields within a data object. When a cache miss occurs, the cache may begin loading portions of a requested data object from various data sources. Instead of waiting for the entire object to load to change the object state to “valid,” the cache may incrementally update the state through various levels of validity based on the user role of the request. When a portion of the data object used by a low-level user role is received, the object state can be upgraded to be valid for that user role while data for higher-level user roles continues to load. The portion of the data object can then be sent to the low-level user roles without waiting for the rest of the data object to load.