Patent classifications
G06F12/0808
TECHNIQUES FOR EFFICIENTLY TRANSFERRING DATA TO A PROCESSOR
A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.
Safe management of data storage using a volume manager
A method, system, and computer program product for safe management of data storage using a VM are provided in the illustrative embodiments. An I/O request is received from the VM. A determination is made whether the I/O request requests a data manipulation on the data storage in an address range that overlaps with an address range of a VM signature stored on the data storage. In response to determining that the address range of the data manipulation overlaps with the address range of the VM signature, a determination is made whether an identifier of the VM matches an identifier of a second VM associated with the signature. In response to determining that the identifier of the VM does not match the identifier of the second VM, the I/O request is failed, thereby preventing an unsafe overwriting of the signature on the data storage.
Maintaining cache consistency in a cache for cache eviction policies supporting dependencies
For maintaining consistency for a cache that contains dependent objects in a computing environment, object dependencies for cached objects are managed by defining and maintaining object dependency lists for each one of the cached objects for identifying objects upon which the cached objects are dependent. Maintaining cache consistency for 2 types of cache eviction policies is supported by maintaining an object dependency lists for each one of the cached objects for identifying objects dependent upon the cached object. Each of the objects in an object dependency list is updated when the object is updated.
Synchronizing updates of page table status indicators and performing bulk operations
A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.
Synchronizing updates of page table status indicators and performing bulk operations
A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.
Cache coherence shared state suppression
A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
Cache coherence shared state suppression
A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.
System and method for pre-operating system memory map management to minimize operating system failures
A method includes booting an information handling system, providing by an EFI of the information handling system a memory segment for a first EFI type memory access, reserving a first portion of the segment from access by an operating system of the information handling system, determining a size of the first portion, determining a size of a second portion of the segment based upon the size of the first portion, allocating a third portion of the segment for the first EFI type memory access, the third portion including the first portion and the second portion, and passing a memory map to the operating system, the memory map including the third portion, wherein the third portion is reserved from access by the operating system.
Utility-based invalidation propagation scheme selection for distributed cache consistency
A computerized method for dynamic consistency management of server side cache management units in a distributed cache, comprising: updating a server side cache management unit by a client; assigning each of a plurality of server side cache management units to one of a plurality of propagation topology groups according to an analysis of a plurality of cache usage measurements thereof, each of said propagation topology groups is associated with a different write request propagation scheme; and managing client update notifications of members of each of said propagation topology groups according to the respective said different write request propagation scheme which is associated therewith.
APPARATUS AND METHOD USING PLURALITY OF PHYSICAL ADDRESS SPACES
Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.