A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

Restricting peripheral device protocols in confidential compute architectures, the method including: receiving a first address translation request from a peripheral device supporting a first protocol, wherein the first protocol supports cache coherency between the peripheral device and a processor cache; determining that a confidential compute architecture is enabled; and providing, in response to the first address translation request, a response including an indication to the peripheral device to not use the first protocol.

Cache memory requirements between normal and peak operation may vary by two orders of magnitude or more. A cache memory management system for multi-tenant computing environments monitors memory requests and uses a pattern matching classifier to generate patterns which are then delivered to a neural network. The neural network is trained to predict near-future cache memory performance based on the current memory access patterns. An optimizer allocates cache memory among the tenants to ensure that each tenant has sufficient memory to meet its required service levels while avoiding the need to provision the computing environment with worst-case scenario levels of cache memory. System resources are preserved while maintaining required performance levels.

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.

A method for transferring packets of a communication protocol via a memory-based interface between two processing units. The method includes providing, in each of the processing units, a send area including a read index section, a write index section, and a send buffer, and a receive area including a read index section, a write index section and a receive buffer. Each processing unit repeats as sending steps: reading a read index from the receive area; writing at least one send packet into the send buffer (from a starting write address to an ending write address, the ending write address maximally corresponding to a buffer address assigned to the read read index, and writing a changed write index into the send area.

A method for transferring packets of a communication protocol via a memory-based interface between two processing units. The method includes providing, in each of the processing units, a send area including a read index section, a write index section, and a send buffer, and a receive area including a read index section, a write index section and a receive buffer. Each processing unit repeats as sending steps: reading a read index from the receive area; writing at least one send packet into the send buffer (from a starting write address to an ending write address, the ending write address maximally corresponding to a buffer address assigned to the read read index, and writing a changed write index into the send area.

Aspects of a storage device including a memory and a controller are provided. The controller may receive a prefetch request to retrieve data for a host having a promoted stream. The controller may access a frozen time table indicating hosts for which data has been prefetched and frozen times associated with the host and other hosts. The controller can determine whether the host has a higher priority over other hosts included in the frozen time table based on corresponding frozen times and data access parameters associated with the host. The controller may determine to prefetch the data for the host in response to the prefetch request when the host has a higher priority than the other hosts. The controller can receive a host read command associated with the promoted stream from the host and provide the prefetched data to the host in response to the host read command.

An apparatus includes multiple processors including respective cache memories, the cache memories configured to cache cache-entries for use by the processors. At least a processor among the processors includes cache management logic that is configured to (i) receive, from one or more of the other processors, cache-invalidation commands that request invalidation of specified cache-entries in the cache memory of the processor (ii) mark the specified cache-entries as intended for invalidation but defer actual invalidation of the specified cache-entries, and (iii) upon detecting a synchronization event associated with the cache-invalidation commands, invalidate the cache-entries that were marked as intended for invalidation.