Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

Techniques are disclosed relating to multi-block fetches for cache misses. In some embodiments, cache tag circuitry maintains a tag value that is shared by multiple cache blocks. In response to a miss, the cache may initiate a fetch request to a next level cache or memory. Aggregation circuitry may aggregate multiple fetch requests for cache blocks that share the tag value and fetch circuitry may initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated multiple fetch requests. In various embodiments, disclosed techniques may improve performance (e.g., by reducing fetch bus transactions), reduce power consumption, or both, relative to traditional techniques.

A system and method for distributing data over a plurality of remote storage nodes. Data are split into segments and each segment is encoded into a number of codeword chunks. None of the codeword chunks contains any of the segments. Each codeword chunk is packaged with at least one encoding parameter and identifier, and metadata are generated for at least one file and for related segments of the at least one file. The metadata contains information to reconstruct from the segments, and information for reconstructing from corresponding packages. Further, metadata are encoded into package(s), and correspond to a respective security level and a protection against storage node failure. A plurality of packages are assigned to remote storage nodes to optimize workload distribution. Each package is transmitted to at least one respective storage node as a function iteratively accessing and retrieving the packages of metadata and file data.

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

An arithmetic processing device including: request issuing units configured to issue an access request to a storage; and banks each of which includes: a first cache area including first entries; a second cache area including second entries; a control unit; and a determination unit that determines a cache hit or a cache miss for each of the banks, wherein the control unit performs: in response that the access requests simultaneously received from the request issuing units make the cache miss, storing the data, which is read from the storage device respectively by the access requests, in one of the first entries and one of the second entries; and in response that the access requests simultaneously received from the request issuing units make the cache hit in the first and second cache areas, outputting the data retained in the first and second entries, to each of issuers of the access requests.

Apparatuses, systems, and techniques to control operation of a memory cache. In at least one embodiment, cache guidance is specified within application source code by associating guidance with declaration of a memory block, and then applying specified guidance to source code statements that access said memory block.

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.