A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

A system and method for providing dynamic information virtualization (DIV) is disclosed. According to one embodiment, a device includes a dynamic optimization manager (DOM), a process and memory manager (PMM), a memory, and a host device driver. The device starts virtual functions after booting to allow a virtual machine (VM) running a guest operating system to identify the virtual functions and load virtual drivers of the virtual functions. The PMM allocates a unified cache from the memory to facilitate coherent access to information from storage and network resources by the VM. The host device driver enables a guest process in the VM to access the information stored in the unified cache in a secure and isolated manner.

A system and method for providing dynamic information virtualization (DIV) is disclosed. According to one embodiment, a device includes a dynamic optimization manager (DOM), a process and memory manager (PMM), a memory, and a host device driver. The device starts virtual functions after booting to allow a virtual machine (VM) running a guest operating system to identify the virtual functions and load virtual drivers of the virtual functions. The PMM allocates a unified cache from the memory to facilitate coherent access to information from storage and network resources by the VM. The host device driver enables a guest process in the VM to access the information stored in the unified cache in a secure and isolated manner.

Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.

Systems, methods, and apparatus related to a memory system that manages an interface for a volatile memory device and a non-volatile memory device to control memory system power. In one approach, a controller evaluates a demand on memory performance. If the demand of a current computation task needed by the host is high, a DRAM device is powered-up to meet the demand. Otherwise, if the non-volatile memory device is adequate to meet the demand, the DRAM memory is partially or fully-powered down to save power. In another approach, a task performed for a host device uses one or more resources of a first memory device (e.g., DRAM). A performance capability of a second memory device (e.g., NVRAM) is determined. A controller of the memory system determines whether the performance capability of the second memory device is adequate to service the task. In response to determining that the performance capability is adequate, the controller changes a mode of operation of the memory system so that one or more resources of the second memory device are used to service the task.

Interleaved cache controllers with shared metadata are disclosed and described. A memory system may comprise a plurality of cache controllers and a metadata store interconnected by a metadata store fabric. The metadata store receives information from at least one of the plurality of cache controllers, a portion of which is stored as shared distributed metadata. The metadata store provides shared access of the shared distributed metadata hosted to the plurality of cache controllers

In some examples, a media controller includes a buffer and controller circuitry. The controller circuitry may receive, from a memory device linked to the media controller, an indication of a number of memory subunits that the memory device is divided into. The controller circuitry may also allocate, within the buffer, a number of logical memory buffers for the memory device greater than the number of memory subunits and indicate to a memory controller that a number of memory units accessible for the memory device is the number of logical memory buffers.

A cache memory device is provided in the disclosure. The cache memory device includes a first AGC, a compression circuit, a second AGC, a virtual tag array, and a comparator circuit. The first AGC generates a virtual address based on a load instruction. The compression circuit obtains the higher part of the virtual address and generates a target hash value based on the higher part of the virtual address. The second AGC generates the lower part of the virtual address based on the load instruction. The virtual tag array obtains the lower part and selects a set of memory units. The comparator circuit compares the target hash value to a hash value stored in each memory unit of the set of memory units. When the comparator circuit generates the virtual tag miss signal, the comparator circuit transmits the virtual tag miss signal to the reservation station.

A cache memory device is provided in the disclosure. The cache memory device includes a first AGC, a compression circuit, a second AGC, a virtual tag array, and a comparator circuit. The first AGC generates a virtual address based on a load instruction. The compression circuit obtains the higher part of the virtual address and generates a target hash value based on the higher part of the virtual address. The second AGC generates the lower part of the virtual address based on the load instruction. The virtual tag array obtains the lower part and selects a set of memory units. The comparator circuit compares the target hash value to a hash value stored in each memory unit of the set of memory units. When the comparator circuit generates the virtual tag miss signal, the comparator circuit transmits the virtual tag miss signal to the reservation station.

An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.