A storage system has volatile memory for use as a cache and can extend the available caching space by using a host memory buffer (HMB) in a host. However, because accesses to the HMB involve going through a host interface, there may be latencies in accessing the HMB, To reduce access latencies, the storage system views the volatile memory and the HMB as a two-level cache. In one use case, the storage system decides whether to store a logical-to-physical address table in the volatile memory or in the HMB based on a prediction of the likelihood that the table will be updated. If the likelihood for an update is above a threshold, the table is stored in the volatile memory, thereby eliminating the access latencies that would be encountered if the table needs to be updated and is stored in the HMB.

A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.

Power consumption can be reduced by selective memory chip hibernation. For example, a computing device can allocate first data associated with a first processing operation of a user device to a first chip of a dynamic random access memory (DRAM) of the user device. The computing device can allocate second data associated with a second processing operation of the user device to a second chip of the DRAM of the user device. The computing device can determine the first processing operation has been inactive for a predetermined period of time and migrate the first data from the first chip of the DRAM to a storage device of the user device. The computing device can hibernate the first chip of the DRAM while maintaining power to the second chip of the DRAM for continuing to perform the second processing operation.

A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends an update data chunk obtained from to-be-written data to a corresponding storage node. The storage node does not directly update, based on the received update data chunk, a data block stored in a storage device of the storage node, but store the update data chunk into a non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node for backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends an update data chunk obtained from to-be-written data to a corresponding storage node. The storage node does not directly update, based on the received update data chunk, a data block stored in a storage device of the storage node, but store the update data chunk into a non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node for backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

Systems, apparatuses, and methods related to three tiered hierarchical memory systems are described herein. A three tiered hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example apparatus may include a persistent memory, and one or more non-persistent memories configured to map an address associated with an input/output (I/O) device to an address in logic circuitry prior to the apparatus receiving a request from the I/O device to access data stored in the persistent memory, and map the address associated with the I/O device to an address in a non-persistent memory subsequent to the apparatus receiving the request and accessing the data.

Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.

Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.

Methods, systems, and devices for maintaining sequentiality for media management of a memory sub-system are described. A plurality of read commands in connection with a set of media management operations for a plurality of transfer units are issued according to a read sequence. A plurality of entries associated with the set of media management operations are stored. A plurality of write commands in connection with the set of media management operations are issued based on the plurality of entries of the read sequence.

Latency in a node-based compute-near-memory system can be problematic. A solution to the problem can include or use a dedicated software-based cache at each node. The cache can be configured to store information received from each of the other nodes in the system. In an example, the cache can be populated during a breadth first search algorithm to store frontier information from each of the other nodes.