The present technology relates to a storage device that allows access to the storage device without accessing a main memory of a host by allocating a portion of a mapping area of a buffer memory to a cache area. The storage device includes a memory device including a plurality of memory cells, a memory controller configured to control an operation performed on the memory device, and a buffer memory including a mapping area and a cache area in which mapping data indicating a mapping relationship between a logical block address and a physical block address corresponding to the operation is stored. The buffer memory allocates a portion of the mapping area to the cache area according to an allocation request received from a host, and stores data except for the mapping data in the cache area.

Techniques for providing an overlap data buffer to store portions of tiles between passes of chained layers of a neural network are described. One accelerator circuit includes one or more processing units to execute instructions corresponding to the chained layers in multiple passes. In a first pass, the processing unit(s) receives a first input tile of an input feature map from a primary buffer and performs a first operation on the first input tile to obtain a first output tile. The processing unit stores the first output tile in the primary buffer and identifies a portion of the first output tile as corresponding to overlap data between tiles of the input feature map. The processing unit stores the portion in a secondary buffer. In a second pass, the processing unit retrieves the portion to avoid fetching the portion that overlaps and computing the overlap data again.

A method, a system, and a computer program product for placement or storage of data structures in memory/storage locations. A type of a data structure for storing data and a type of data access to the data structure are determined. The type of data access includes a first and a second type of data access. A frequency of each type of access to each type of data structure accessed by a query is determined. Using the determined frequency, a number of first type of data accesses to the data structure is compared to a number of second type of accesses to the data structure. The numbers of first and second types of data access are compared to a predetermined threshold percentage of a total number of data accesses to the data structure. Based on the comparisons, a physical memory location for storing data is determined.

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

Disclosed herein is a computer-implemented method for storing Merkle tree data in memory. The Merkle tree data comprising uncle node data, first nephew node data and second nephew node data. The computer implemented method comprises determining a first nephew node memory address, determining a second nephew node memory address, storing the uncle node data at the uncle node memory address, storing the first nephew node data at the first nephew node memory address, and storing the second nephew node data at the second nephew node memory address. The first nephew node memory address is less than the uncle node memory address and the second nephew node memory address is greater than the uncle node memory address, or the first nephew node memory address is greater than the uncle node memory address and the second nephew node memory address is less than the uncle node memory address.

Managing a cache includes parsing a physical address of a data block to determine a partition identifier (ID) and a tag; the partition ID compared against a partition table storing partition IDs. The partition table indicates at least one way partition and at least one set partition corresponding to the partition ID. Based on the partition table, a way partition is determined at which to store the data block, corresponding to a subset of columns of a cache and, based on the partition table and the tag, a set partition is determined at which to store the data block, corresponding to a subset of rows of the cache. A cache address is generated for the data block within a first region of the cache corresponding to an intersection of the way partition and the set partition. The data block is stored to the cache according to the cache address.

Managing a cache includes parsing a physical address of a data block to determine a partition identifier (ID) and a tag; the partition ID compared against a partition table storing partition IDs. The partition table indicates at least one way partition and at least one set partition corresponding to the partition ID. Based on the partition table, a way partition is determined at which to store the data block, corresponding to a subset of columns of a cache and, based on the partition table and the tag, a set partition is determined at which to store the data block, corresponding to a subset of rows of the cache. A cache address is generated for the data block within a first region of the cache corresponding to an intersection of the way partition and the set partition. The data block is stored to the cache according to the cache address.

A virtualized system is provided. The virtualized system includes: a memory device; a processor configured to provide a virtualization environment; a direct memory access device configured to perform a function of direct memory access to the memory device; and a memory management circuit configured to manage a core access of the processor to the memory device and a direct access of the direct memory access device to the memory device. The processor is further configured to provide: a plurality of guest operating systems that run independently from each other on a plurality of virtual machines of the virtualization environment; and a hypervisor configured to control the plurality of virtual machines in the virtualization environment and control the memory management circuit to block the direct access when a target guest operating system controlling the direct memory access device, among the plurality of guest operating systems is rebooted.

A virtualized system is provided. The virtualized system includes: a memory device; a processor configured to provide a virtualization environment; a direct memory access device configured to perform a function of direct memory access to the memory device; and a memory management circuit configured to manage a core access of the processor to the memory device and a direct access of the direct memory access device to the memory device. The processor is further configured to provide: a plurality of guest operating systems that run independently from each other on a plurality of virtual machines of the virtualization environment; and a hypervisor configured to control the plurality of virtual machines in the virtualization environment and control the memory management circuit to block the direct access when a target guest operating system controlling the direct memory access device, among the plurality of guest operating systems is rebooted.