An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

A memory controller includes a mapping data control unit configured to interrupt the generation of the additional mapping data, when during generation of additional mapping data, an operation for an address identical to a logical block address in the additional mapping data is performed, and to generate dummy mapping data. The additional mapping data may include mapping information indicating a mapping relationship between a logical block address and a physical block address.

A memory controller includes a mapping data control unit configured to interrupt the generation of the additional mapping data, when during generation of additional mapping data, an operation for an address identical to a logical block address in the additional mapping data is performed, and to generate dummy mapping data. The additional mapping data may include mapping information indicating a mapping relationship between a logical block address and a physical block address.

The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a cached mapping table area and has a root mapping table. The processor determines whether a first node mapping table of the node mapping tables is temporarily stored in the cached mapping table area according to the root mapping table. In response to the first node mapping table is temporarily stored in the cached mapping table area, the processor accesses data according to the first node mapping table in the cached mapping table area, marks the modified first node mapping table through an asynchronous index identifier, and writes back the modified first node mapping table from the cached mapping table area to the memory array.

The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a cached mapping table area and has a root mapping table. The processor determines whether a first node mapping table of the node mapping tables is temporarily stored in the cached mapping table area according to the root mapping table. In response to the first node mapping table is temporarily stored in the cached mapping table area, the processor accesses data according to the first node mapping table in the cached mapping table area, marks the modified first node mapping table through an asynchronous index identifier, and writes back the modified first node mapping table from the cached mapping table area to the memory array.

An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.

The system can receive data to be written to a non-volatile memory in the distributed storage system. The received data can include a plurality of input segments. The system can assign consecutive logical block addresses (LBAs) to the plurality of input segments. The system can then compress the plurality of input segments to generate a plurality of fixed-length compressed segments, with each fixed-length compressed segment aligned with a physical block address (PBA) in a set of PBAs. The system compresses the plurality of input segments to enable an efficient use of storage capacity in the non-volatile memory. Next, the system can write the plurality of fixed-length compressed segments to a corresponding set of PBAs in the non-volatile memory. The system can then create, in a data structure, a set of entries which map the LBAs of the input segments to the set of PBAs. This data structure can be used later by the system when processing a read request including a LBA.

The system can receive data to be written to a non-volatile memory in the distributed storage system. The received data can include a plurality of input segments. The system can assign consecutive logical block addresses (LBAs) to the plurality of input segments. The system can then compress the plurality of input segments to generate a plurality of fixed-length compressed segments, with each fixed-length compressed segment aligned with a physical block address (PBA) in a set of PBAs. The system compresses the plurality of input segments to enable an efficient use of storage capacity in the non-volatile memory. Next, the system can write the plurality of fixed-length compressed segments to a corresponding set of PBAs in the non-volatile memory. The system can then create, in a data structure, a set of entries which map the LBAs of the input segments to the set of PBAs. This data structure can be used later by the system when processing a read request including a LBA.

A method for transferring data may include writing, from a producing device, data to a storage device through an interconnect, determining a consumer device for the data, prefetching the data from the storage device, and transferring, based on the determining, the data to the consumer device through the interconnect. The method may further comprise receiving, at a prefetcher for the storage device, an indication of a relationship between the producing device and the consumer device, and determining the consumer device based on the indication. The method may further comprise placing the data in a stream at the storage device based on the relationship between the producing device and the consumer device. The indication may be provided by an application associated with the consumer device. Receiving the indication may include receiving the indication through a coherent memory protocol for the interconnect.