A request to access data at an address is received from a host system. A tag associated with the address is determined to not be found in first entries in a first content-addressable memory (CAM) or in second entries in a second CAM. Responsive to determining that the tag is not found in the first entries or in the second entries, a particular entry of the first entries that each includes valid data is selected. A determination is made whether the particular entry satisfies a condition indicating that content in the particular entry is to be stored in the second CAM. The content is associated with other data stored in the cache. Responsive to determining that the condition is satisfied, the content of the particular entry is stored in one of the second entries to maintain the data in the cache.

A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

A method includes: providing a DDR interface between a host memory controller and a memory module; and providing a message interface between the host memory controller and the memory module. The memory module includes a non-volatile memory and a DRAM configured as a DRAM cache of the non-volatile memory. Data stored in the non-volatile memory of the memory module is asynchronously accessible by a non-volatile memory controller of the memory module, and data stored in the DRAM cache is directly and synchronously accessible by the host memory controller.

An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

A data processing system 2 includes interconnect circuitry 10 providing a plurality of memory transaction paths between one or more transaction masters, including a processor 4, debugging circuitry 6 and a DMA unit 8, and one or more transaction slaves including a non-volatile memory 12, a DRAM memory 18 and an I/O interface 20. A cache memory 26 is provided between the interconnect circuitry 10 and the non-volatile memory 12. This cache memory 26 may be a two way set associative cache memory. The cache memory 26 may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory 26 and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory 26 upon the cache miss.

A data processing system 2 includes interconnect circuitry 10 providing a plurality of memory transaction paths between one or more transaction masters, including a processor 4, debugging circuitry 6 and a DMA unit 8, and one or more transaction slaves including a non-volatile memory 12, a DRAM memory 18 and an I/O interface 20. A cache memory 26 is provided between the interconnect circuitry 10 and the non-volatile memory 12. This cache memory 26 may be a two way set associative cache memory. The cache memory 26 may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory 26 and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory 26 upon the cache miss.

A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.

A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.