Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

Processing requests may include: receiving a write request from a host at a first node of a system; and servicing the write comprising assigning, by the first node, a sequence identifier to the write request, wherein the sequence identifier is included in a subsequence of identifiers only assignable by the first node, performing in parallel a first operation that stores first data written by the write request in a cache, a second operation that stores a descriptor for the write request in the cache, and a third operation that sends the descriptor (including the sequence identifier) to a peer node of the system; determining by the first node that the first, second and third operations have successfully completed; and responsive to determining the first, second and third operations have successfully completed, sending an acknowledgement from the first node to a host indicating successful completion of the write request.

Processing requests may include: receiving a write request from a host at a first node of a system; and servicing the write comprising assigning, by the first node, a sequence identifier to the write request, wherein the sequence identifier is included in a subsequence of identifiers only assignable by the first node, performing in parallel a first operation that stores first data written by the write request in a cache, a second operation that stores a descriptor for the write request in the cache, and a third operation that sends the descriptor (including the sequence identifier) to a peer node of the system; determining by the first node that the first, second and third operations have successfully completed; and responsive to determining the first, second and third operations have successfully completed, sending an acknowledgement from the first node to a host indicating successful completion of the write request.

A memory system includes a storage medium and a controller. The storage medium includes a plurality of memory regions. The controller stores data corresponding to a write request into a memory region of a random attribute or a memory region of a sequential attribute among the memory regions and to update logical-to-physical (L2P) information corresponding to the stored data, and updates, when storing the data into the memory region of the random attribute, physical-to-logical (P2L) information corresponding to the stored data within a P2L table of the memory region of the random attribute.

A memory system includes a storage medium and a controller. The storage medium includes a plurality of memory regions. The controller stores data corresponding to a write request into a memory region of a random attribute or a memory region of a sequential attribute among the memory regions and to update logical-to-physical (L2P) information corresponding to the stored data, and updates, when storing the data into the memory region of the random attribute, physical-to-logical (P2L) information corresponding to the stored data within a P2L table of the memory region of the random attribute.

A field programmable gate array (FPGA)-based parallel equalization method is provided. The method implements efficient equalization of communication data by means of a parallel pipeline filter structure and through a least mean square (LMS) algorithm capable of dynamically adjusting a step. Firstly, a tap coefficient of an equalization filter is calculated through the LMS algorithm capable of dynamically adjusting an iteration factor. Secondly, the efficiency of FPGA data processing is improved through a multistage pipeline and a multi-channel parallel data processing. According to the present disclosure, in each clock cycle, there are M channels of data inputted into the equalization filter in parallel, and at the same time, there are also M channels of data outputted in parallel, and thus the FPGA can efficiently perform equalization processing on data acquired by a high-speed analog-to-digital converter (ADC) through the parallel pipeline method.

A field programmable gate array (FPGA)-based parallel equalization method is provided. The method implements efficient equalization of communication data by means of a parallel pipeline filter structure and through a least mean square (LMS) algorithm capable of dynamically adjusting a step. Firstly, a tap coefficient of an equalization filter is calculated through the LMS algorithm capable of dynamically adjusting an iteration factor. Secondly, the efficiency of FPGA data processing is improved through a multistage pipeline and a multi-channel parallel data processing. According to the present disclosure, in each clock cycle, there are M channels of data inputted into the equalization filter in parallel, and at the same time, there are also M channels of data outputted in parallel, and thus the FPGA can efficiently perform equalization processing on data acquired by a high-speed analog-to-digital converter (ADC) through the parallel pipeline method.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.

Methods and systems for managing storage of data in a distributed system are disclosed. To manage storage of data in a distributed system, a data processing system may include a network interface controller (NIC). The network interface controller may present emulated storages that may be used for data storage. The emulated storage devices may utilize storage resources of storage devices. Overtime, the data stored in various data storages may be migrated between the data storages. To migrate the data, the NIC may manage the migration process. To do so, the NIC may obtain various access requests (e.g., writes, reads) and process them in a manner that allows for the migration to be transparent. By doing so, migrations that are transparent to compute resources of data processing systems may be completed.