Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

Some aspects of the disclosure relate to a pre-fetch mechanism for a cache line compression system that increases RAM capacity and optimizes overflow area reads. For example, a pre-fetch mechanism may allow the memory controller to pipeline the reads from an area with fixed size slots (main compressed area) and the reads from an overflow area. The overflow area is arranged so that a cache line most likely containing the overflow data for a particular line may be calculated by a decompression engine. In this manner, the cache line decompression engine may fetch, in advance, the overflow area before finding the actual location of the overflow data.

A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.

A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

A cache memory includes a first cache area corresponding to even addresses, and a second cache area corresponding to odd addresses, wherein each of the first and second cache areas includes a plurality of cache sets, and each cache set includes a data set field suitable for storing data corresponding to an address among the even and odd addresses, and a pair field suitable for storing information on a location where data corresponding to an adjacent address which is adjacent to an address corresponding to the stored data is stored.

The present disclosure generally relates to efficient transfer layer packet (TLP) fragmentation in a data storage device. For an unaligned read from host flow, an amount of data sufficient to be aligned is transferred to the memory device from the host while the remainder of the data is stored in cache of the data storage device to be delivered to memory device at a later time. For an unaligned write to host flow, the unaligned data is written to cache and at a later time the cache will be flushed to the host device. In both cases, while the total data would be unaligned, a portion of the data is placed in cache so that the data not placed in cache is aligned. The data in cache is delivered at a later point in time.