An embodiment of an integrated circuit may comprise, coupled to a core, a hardware decompression accelerator, a compressed cache, a processor and communicatively coupled to the hardware decompression accelerator and the compressed cache, and memory and communicatively coupled to the processor, wherein the memory stores microcode instructions which when executed by the processor causes the processor to store a first address to a decompression work descriptor, retrieve a second address where a compressed page is stored in the compressed cache from the decompression work descriptor at the first address in response to an indication of a page fault, and send instructions to the hardware decompression accelerator to decompress the compressed page at the second address. Other embodiments are disclosed and claimed.

The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.

The present disclosure generally relates to effective transport layer packet (TLP) utilization. When the controller of the data storage device generates a request for transferring data to or from the storage device, the request is stored in a merging buffer. The merging buffer may include previously generated requests, where the previously generated requests and the new requests are merged. A timeout counter is initialized for the requests stored in the merging buffer. The timeout counter has a configurable threshold value that corresponds to a weight value, adjusted for latency or bandwidth considerations. When the merged request is greater than the maximum TLP size, the merged request is partitioned, where at least one partition is in the size of the maximum TLP size. The request is sent from the buffer when the request is in the size of the maximum TLP size or when the threshold value is exceeded.

A command indicating a logical address and a length system is received from a host system. One or more memory units in a memory sub-system corresponding to the logical address and the length are identified. An indicator associated with the one or more memory units is set, to indicate that the one or more memory units are invalid. The one or more memory units are excluded from a media management operation performing in the memory sub-system.

A command indicating a logical address and a length system is received from a host system. One or more memory units in a memory sub-system corresponding to the logical address and the length are identified. An indicator associated with the one or more memory units is set, to indicate that the one or more memory units are invalid. The one or more memory units are excluded from a media management operation performing in the memory sub-system.

A digital data processor includes an instruction memory storing instructions specifying a data processing operation and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to perform a table write in response to a look up table initialization instruction by duplicating at least one data element from a source data register to create duplicated data elements, and writing the duplicated data elements to a specified location in a specified number of at least one table and a corresponding location in at least one other table.

A method of operating a storage appliance is provided. The method includes (a) in response to the appliance receiving a first command to perform a first storage operation on a first plurality of blocks, storing a command record for each block of the first plurality in a cache, each command record respectively indicating an address of that block; (b) upon flushing the command record for each block of the first plurality from the cache to persistent storage, storing data of that block at its indicated address; (c) in response to the storage appliance receiving a second command to perform a second storage operation on a second plurality of blocks, storing, in the cache, an aggregated command record that indicates the second storage operation and an address range of the second plurality, the second storage operation representing an identical change to all blocks of the second plurality; and (d) upon flushing the aggregated command record from the cache to the persistent storage, performing the storage operation indicated by the aggregated command record over the address range indicated by the aggregated command record.

A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

According to an embodiment of the present invention, a probability to achieve a purpose is increased in a case where information is intermittently allocated to a plurality of elements. An information processing apparatus according to an embodiment of the present invention is an information processing apparatus that allocates information to respective elements included in a first set and includes an allocator. The allocator uses a first subset and a second subset, and allocates the information to at least one element included in the first subset. The first subset is constituted by elements which are included in the first set and in which information allocation may be performed at a present time. The second subset is constituted by elements which are included in the first set and in which the information allocation is not performed at the present time.

A multi-resolution cache includes a first, second and third cache segments the first segment having a first resolution and the second and third segments having a second resolution, the second resolution less than the first resolution, the first and third cache segments communicatively coupled to an off-chip memory, the first and third cache segments configured to each receive a cache line of data having the first and second resolutions, a fourth and fifth cache segments having the second resolution, a first downscaler communicatively coupled to the first and fourth cache segments configured to reduce the resolution when a first resolution cached data is shifted from the first cache segment to the fourth cache segment, a first upscaler communicatively coupled to the all cache segments that have the second resolution, and is configured to increase the reduced resolution cached data to the first resolution and output it.