The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

Methods, computer program products, and/or systems are provided that perform the following operations: setting a memory buffer having contiguous memory blocks; obtaining a decision tree comprising nodes including split nodes and leaf nodes, wherein each of the split nodes includes at least two child nodes that are ordered according to a likelihood of accessing a child node after each of the split nodes; mapping the nodes onto respective blocks of the memory blocks, each of the memory blocks storing attributes of a corresponding one of the nodes, wherein each of the split nodes and any child nodes of each split node are mapped onto successive blocks, wherein ordered child nodes of a same one of the split nodes are mapped onto successive blocks; executing the nodes by processing the attributes of the nodes as accessed from the memory according to an order of the memory blocks in the memory buffer.

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and prefetch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of prefetch requests in dependence on reception of the trigger.

A storage device is provided to comprise a memory device for storing data, a cache memory device including a first cache memory configured to cache certain data stored in the memory device and a second cache memory configured to store data evicted from the first cache memory, and a memory controller configured to receive a read request for first data from a host, evict second data from the first cache memory based on a reuse distance of the second data, store the second data in the second cache memory, load the first data to the first cache memory, and transmit the first data to the host.

A storage device is provided to comprise a memory device for storing data, a cache memory device including a first cache memory configured to cache certain data stored in the memory device and a second cache memory configured to store data evicted from the first cache memory, and a memory controller configured to receive a read request for first data from a host, evict second data from the first cache memory based on a reuse distance of the second data, store the second data in the second cache memory, load the first data to the first cache memory, and transmit the first data to the host.

The present invention discloses a method and a system for managing cache memory. The system comprising a processor is configured to receive datasets from one or more applications, segregate the received datasets into one or more data blocks, identify a checkpoint from previously created checkpoints stored in a virtual cache corresponding to the one or more data blocks, wherein the checkpoints are previously created based on frequency of repetition of each of the one or more data blocks and association between the each of the one or more data blocks, recall a sequence of previously stored data blocks from main memory based on the identified checkpoint, and send the sequence of previously stored data blocks to the one or more applications for execution, thereby managing cache memory.

The disclosure relates to technology for up-evicting cache lines. An apparatus comprises a hierarchy of caches comprising a first cache having a first cache controller and a second cache having a second cache controller. The first cache controller is configured to store cache lines evicted from a first processor group to the first cache and to down-evict cache lines from the first cache to the second cache. The second cache controller is configured to store cache lines evicted from a second processor group into the second cache, to up-evict a first cache line from the second cache to the first cache in response to an eviction of a second cache line from the second processor group to the second cache, and to provide the up-evicted first cache line from the first cache to the second processor group in response to a request from the second processor group.