A storage device includes a storage controller and a host interface which sends an address translation service request to a host. The host interface includes an address translation cache which stores first address information included in the address translation service request, and an address translation service latency storage which stores latency-related information including a first time until the address translation cache receives an address translation service response corresponding to the address translation service request from the host. After the host interface sends the address translation service request to the host based on the latency-related information including the first time, and after the first time elapses, the storage controller polls the host interface.

The present invention discloses an instruction processing apparatus, including: a first register adapted to store address information; a second register adapted to store address space identification information; a decoder adapted to receive and decode a translation lookaside buffer flush instruction, where the translation lookaside buffer flush instruction indicates that the first register serves as a first operand, and the second register serves as a second operand; and an execution unit coupled to the first register, the second register, and the decoder and executing the decoded translation lookaside buffer flush instruction, so as to acquire address information from the first register, to acquire address space identification information from the second register, and to broadcast the acquired address, information and address space identification information on a bus coupled to the instruction processing apparatus, so that another processing unit coupled to the bus performs purging on a translation lookaside buffer, corresponding to the address information, in an address space indicated by the address space identification information. The present invention also discloses a corresponding instruction processing method, a computing system, and a system-on-chip.

The present invention discloses an instruction processing apparatus, including: a first register adapted to store address information; a second register adapted to store address space identification information; a decoder adapted to receive and decode a translation lookaside buffer flush instruction, where the translation lookaside buffer flush instruction indicates that the first register serves as a first operand, and the second register serves as a second operand; and an execution unit coupled to the first register, the second register, and the decoder and executing the decoded translation lookaside buffer flush instruction, so as to acquire address information from the first register, to acquire address space identification information from the second register, and to broadcast the acquired address, information and address space identification information on a bus coupled to the instruction processing apparatus, so that another processing unit coupled to the bus performs purging on a translation lookaside buffer, corresponding to the address information, in an address space indicated by the address space identification information. The present invention also discloses a corresponding instruction processing method, a computing system, and a system-on-chip.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Systems and methods are provided for decoding data read from non-volatile storage devices. A method may comprise receiving a chunk of data read from a physical location of a non-volatile storage device and searching a memory for soft information associated with the physical location using a unique identifier associated with the physical location. The soft information may be generated from one or more previous decoding processes on previous data from the physical location. The method may further comprise retrieving the soft information identified by the unique identifier associated with the physical location from the memory, decoding the chunk of data with the soft information indicating reliability of bits in the chunk of data and updating the soft information with decoding information generated during the decoding.

In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

An arbiter gathers translation invalidation requests assigned to state machines of a lower-level cache into a set for joint handling in a processor core. The gathering includes selection of one of the set of gathered translation invalidation requests as an end-of-sequence (EOS) request. The arbiter issues to the processor core a sequence of the gathered translation invalidation requests terminating with the EOS request. Based on receipt of each of the gathered requests, the processor core invalidates any translation entries providing translation for the addresses specified by the translation invalidation requests and marks memory-referent requests dependent on the invalidated translation entries. Based on receipt of the EOS request and in response to all of the marked memory-referent requests draining from the processor core, the processor core issues a completion request to the lower-level cache indicating completion of servicing by the processor core of the set of gathered translation invalidation requests.

An arbiter gathers translation invalidation requests assigned to state machines of a lower-level cache into a set for joint handling in a processor core. The gathering includes selection of one of the set of gathered translation invalidation requests as an end-of-sequence (EOS) request. The arbiter issues to the processor core a sequence of the gathered translation invalidation requests terminating with the EOS request. Based on receipt of each of the gathered requests, the processor core invalidates any translation entries providing translation for the addresses specified by the translation invalidation requests and marks memory-referent requests dependent on the invalidated translation entries. Based on receipt of the EOS request and in response to all of the marked memory-referent requests draining from the processor core, the processor core issues a completion request to the lower-level cache indicating completion of servicing by the processor core of the set of gathered translation invalidation requests.

An example memory array page table walk can include using an array of memory cells configured to store a page table. The page table walk can include using sensing circuitry coupled to the array. The page table walk can include using a controller coupled to the array. The controller can be configured to operate the sensing circuitry to determine a physical address of a portion of data by accessing the page table in the array of memory cells. The controller can be configured to operate the sensing circuitry to cause storing of the portion of data in a buffer.