A method includes storing a first block of main memory in a cache line of a direct-mapped cache, storing a first tag in a current tag field of the cache line, wherein the first tag identifies a first memory address for the first block of main memory, and storing a second tag in a previous miss tag field of the cache line in response to receiving a memory reference having a tag that does not match the tag stored in the current tag field. The second tag identifies a second memory address for a second block of main memory, and the first and second blocks are both mapped to the cache line. The method may further include storing a binary value in a last reference bit field to indicate whether the most recently received memory reference was directed to the current tag field or previous miss tag field.

Various cache replacement policies are described whose goals are to identify items for eviction from the cache that are not accessed often and to identify items stored in the cache that are regularly accessed that should be maintained longer in the cache. In particular, the cache replacement policies are useful for workloads that have a strong temporal locality, that is, items that are accessed very frequently for a period of time and then quickly decay in terms of further accesses. In one embodiment, a variation on the traditional least recently used caching algorithm uses a reuse period or reuse distance for an accessed item to determine whether the item should be promoted in the cache queue. In one embodiment, a variation on the traditional two queue caching algorithm evicts items from the cache from both an active queue and an inactive queue.

Various cache replacement policies are described whose goals are to identify items for eviction from the cache that are not accessed often and to identify items stored in the cache that are regularly accessed that should be maintained longer in the cache. In particular, the cache replacement policies are useful for workloads that have a strong temporal locality, that is, items that are accessed very frequently for a period of time and then quickly decay in terms of further accesses. In one embodiment, a variation on the traditional least recently used caching algorithm uses a reuse period or reuse distance for an accessed item to determine whether the item should be promoted in the cache queue. In one embodiment, a variation on the traditional two queue caching algorithm evicts items from the cache from both an active queue and an inactive queue.

Various embodiments for grouping tracks for destaging by a processor device in a computing environment are provided. Tracks are selected for destaging from a least recently used (LRU) list and the selected tracks are moved to a destaging wait list. One of the selected tracks is selected from the destaging wait list and the selected tracks are grouped for destaging. A first track and a last track are located from the group of selected tracks of the destaging wait list. The destaging is commenced from the first track in the group of selected tracks. A track is added to the group of selected tracks if the track is one of modified and located in a cache, otherwise, a next one of the selected tracks in the group of selected tracks is moved to.

Various embodiments for grouping tracks for destaging by a processor device in a computing environment are provided. Tracks are selected for destaging from a least recently used (LRU) list and the selected tracks are moved to a destaging wait list. One of the selected tracks is selected from the destaging wait list and the selected tracks are grouped for destaging. A first track and a last track are located from the group of selected tracks of the destaging wait list. The destaging is commenced from the first track in the group of selected tracks. A track is added to the group of selected tracks if the track is one of modified and located in a cache, otherwise, a next one of the selected tracks in the group of selected tracks is moved to.

According to one embodiment, a memory system includes a non-volatile memory array with a plurality of memory cells. Each memory cell is a multilevel cell to which multibit data can be written. The non-volatile memory array includes a first storage region in which the multibit data of a first bit level is written and a second storage region in which data of a second bit level less than the first bit level is written. A memory controller is configured to move pieces of data from the first storage region to the second storage region based on the number of data read requests for the pieces of data received over a period of time or on external information received from a host device that sends read requests.

According to one embodiment, a memory system includes a non-volatile memory array with a plurality of memory cells. Each memory cell is a multilevel cell to which multibit data can be written. The non-volatile memory array includes a first storage region in which the multibit data of a first bit level is written and a second storage region in which data of a second bit level less than the first bit level is written. A memory controller is configured to move pieces of data from the first storage region to the second storage region based on the number of data read requests for the pieces of data received over a period of time or on external information received from a host device that sends read requests.

Methods and systems for a device coupled to a computing device are provided. As an example, one method includes receiving a request for processing an address list control block (ALCB) by an ALCB offload engine of an adapter coupled to a computing device; determining by the ALCB offload engine if the ALCB is located at a cache managed by a cache controller of the ALCB engine; forwarding the ALCB to an address computation module that determines an address of a memory location of the computing device, where the ALCB stores the address of the memory location in an address list; generating a direct memory access (DMA) request to retrieve the ALCB from an adapter memory, when the ALCB is not located at the cache; and storing the ALCB at the cache, after the ALCB is received in response to the DMA request.

A data processing system includes an upper level cache memory and a lower level cache memory employing different replacement policies. The lower level cache memory provides a respective one of a plurality of counters for each of a plurality of cache lines in a particular congruence class. The lower level cache memory initializes a counter value for a cache line in the particular congruence class that was castout from the upper level cache memory based on an indication of whether the cache line was accessed in the upper level cache memory following installation in the upper level cache memory. The lower level cache memory selects a victim cache line from among the plurality of cache lines in the particular congruence class for eviction from the lower level cache memory by reference to counter values of the plurality of counters.

A data processing system includes an upper level cache memory and a lower level cache memory employing different replacement policies. The lower level cache memory provides a respective one of a plurality of counters for each of a plurality of cache lines in a particular congruence class. The lower level cache memory initializes a counter value for a cache line in the particular congruence class that was castout from the upper level cache memory based on an indication of whether the cache line was accessed in the upper level cache memory following installation in the upper level cache memory. The lower level cache memory selects a victim cache line from among the plurality of cache lines in the particular congruence class for eviction from the lower level cache memory by reference to counter values of the plurality of counters.