A hybrid hierarchical cache is implemented at the same level in the access pipeline, to get the faster access behavior of a smaller cache and, at the same time, a higher hit rate at lower power for a larger cache, in some embodiments. A split cache at the same level in the access pipeline includes two caches that work together. In the hybrid, split, low level cache (e.g., L1) evictions are coordinated locally between the two L1 portions, and on a miss to both L1 portions, a line is allocated from a larger L2 cache to the smallest L1 cache.

A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set; for each parcel of a plurality of parcels, a parcel specifier specifies: a subset of ways of the N ways included in the parcel. The subsets of ways of parcels associated with a selected set are mutually exclusive; a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes. For each memory access, the allocation unit: selects the parcel specifier in response to the memory access; and uses the replacement scheme associated with the parcel to allocate into the subset of ways of the selected set included in the parcel.

A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set; for each parcel of a plurality of parcels, a parcel specifier specifies: a subset of ways of the N ways included in the parcel. The subsets of ways of parcels associated with a selected set are mutually exclusive; a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes. For each memory access, the allocation unit: selects the parcel specifier in response to the memory access; and uses the replacement scheme associated with the parcel to allocate into the subset of ways of the selected set included in the parcel.

A a set associative cache memory, comprising: an array of storage elements arranged as N ways; an allocation unit that allocates the storage elements of the array in response to memory accesses that miss in the cache memory; wherein each of the memory accesses has an associated memory access type (MAT) of a plurality of predetermined MATs, wherein the MAT is received by the cache memory; a mapping that, for each MAT of the plurality of predetermined MATs, associates the MAT with a subset of one or more ways of the N ways; wherein for each memory access of the memory accesses, the allocation unit allocates into a way of the subset of one or more ways that the mapping associates with the MAT of the memory access; and wherein the mapping is dynamically updatable during operation of the cache memory.

Exemplary methods, apparatuses, and systems receive from a client a request to access data from a client. Whether metadata for the data is stored in a first caching layer is determined. In response to the metadata for the data not being stored in the first caching layer, it is determined if the data is stored in the second caching layer. In response to determining that the data is stored in the second caching layer, the data is retrieved from the second caching layer. In response to determining that the data is not stored in the second caching layer, writing of the data to the second caching layer is bypassed. The retrieved data is sent to the client.

An arithmetic processing device includes a core, and a first control circuit that controls a memory request issued by the processing core. The first control circuit includes a miss access control unit with input entries that assigns an input entry to the memory request to control a process of the memory request, and a control pipeline circuit that performs a cache hit determination and issues a memory request to the miss access control unit in a case of cache miss. The control pipeline circuit includes a speculative request control unit that issues a speculative memory request to the miss access control unit before the cache hit determination is performed, cancels the issued speculative memory request in a case of cache hit, and more suppresses issuing the speculative memory request when the number of input entries assigned to the canceled speculative memory request increases.

An arithmetic processing device includes a core, and a first control circuit that controls a memory request issued by the processing core. The first control circuit includes a miss access control unit with input entries that assigns an input entry to the memory request to control a process of the memory request, and a control pipeline circuit that performs a cache hit determination and issues a memory request to the miss access control unit in a case of cache miss. The control pipeline circuit includes a speculative request control unit that issues a speculative memory request to the miss access control unit before the cache hit determination is performed, cancels the issued speculative memory request in a case of cache hit, and more suppresses issuing the speculative memory request when the number of input entries assigned to the canceled speculative memory request increases.

A method for maintaining intelligent write ordering in an asynchronous data replication system is disclosed. In one embodiment, such a method includes performing the following, in order, for each extent of each rank of the primary storage device: (1) determining which primary volume the extent is associated with on the primary storage device; (2) if the primary volume that is associated with the extent is in a mirroring relationship with a corresponding secondary volume on the secondary storage device, scanning an out-of sync bitmap associated with the primary volume; and (3) sending, from the primary volume to the secondary volume, tracks in the extent having corresponding bits set in the out-of sync bitmap. A corresponding system and computer program product are also disclosed.

An information processing apparatus includes a processor. The processor configured to allocate, to a process, a first number of first divided regions from among a plurality of divided regions obtained by division of a cache, and determine, based on an address of each data block corresponding to the process and the first number, a storage destination of the data block corresponding to the process from among the first divided regions. The processor configured to determine a second number that is a divisor of the first number, identify, for the individual first divided regions after the reduction, second divided regions from among the first divided regions before the reduction, determine data blocks to be stored in the individual first divided regions after the reduction by allocating data blocks to the first divided regions after the reduction from the corresponding second divided regions in ascending order of purging order.

An information processing apparatus includes a processor. The processor configured to allocate, to a process, a first number of first divided regions from among a plurality of divided regions obtained by division of a cache, and determine, based on an address of each data block corresponding to the process and the first number, a storage destination of the data block corresponding to the process from among the first divided regions. The processor configured to determine a second number that is a divisor of the first number, identify, for the individual first divided regions after the reduction, second divided regions from among the first divided regions before the reduction, determine data blocks to be stored in the individual first divided regions after the reduction by allocating data blocks to the first divided regions after the reduction from the corresponding second divided regions in ascending order of purging order.