A cache may store critical cache lines and non-critical cache lines, and may attempt to retain critical cache lines in the cache by, for example, favoring the critical cache lines in replacement data updates, retaining the critical cache lines with a certain probability when victim cache blocks are being selected, etc. Criticality values may be retained at various levels of the cache hierarchy. Additionally, accelerated eviction may be employed if the threads previously accessing the critical cache blocks are viewed as dead.

Methods and apparatus for starvation mitigation for associative cache designs. A memory controller employs an associative cache to cache physical page addresses and logic to monitor a level of cache contention. When the contention reaches a critical level where QoS can’t be guaranteed, a backpressure mechanism is triggered by cache contention mitigation logic to prevent new memory access commands from a host from entering a command pipeline. The mitigation logic maintains the backpressure until the monitoring logic indicates that the contention has resolved. The levels of contention that triggers and releases the backpressure may be set using configurable control registers. A starvation counter is incremented when a cache slot cannot be allocated for a command and decremented when a replayed command is allocated a slot. A starvation count is evaluated to determine when backpressure should be triggered and released.

Methods and apparatus for starvation mitigation for associative cache designs. A memory controller employs an associative cache to cache physical page addresses and logic to monitor a level of cache contention. When the contention reaches a critical level where QoS can’t be guaranteed, a backpressure mechanism is triggered by cache contention mitigation logic to prevent new memory access commands from a host from entering a command pipeline. The mitigation logic maintains the backpressure until the monitoring logic indicates that the contention has resolved. The levels of contention that triggers and releases the backpressure may be set using configurable control registers. A starvation counter is incremented when a cache slot cannot be allocated for a command and decremented when a replayed command is allocated a slot. A starvation count is evaluated to determine when backpressure should be triggered and released.

The described technology is generally directed towards detecting and propagating changes that affect information maintained in a cache. Data may be pre-cached in advance of its actual need, however such data can change, including in various different source locations. A change monitoring/signaling service detects relevant changes and publishes change events to downstream listeners, including to a cache population service that updates pre-cache data as needed in view of such data changes. Per-user-specific data also may be pre-cached, such as when a user logs into a data service.

The described technology is generally directed towards detecting and propagating changes that affect information maintained in a cache. Data may be pre-cached in advance of its actual need, however such data can change, including in various different source locations. A change monitoring/signaling service detects relevant changes and publishes change events to downstream listeners, including to a cache population service that updates pre-cache data as needed in view of such data changes. Per-user-specific data also may be pre-cached, such as when a user logs into a data service.

In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.

In some examples, performance counters for computer memory may include ascertaining a request associated with a memory address range of computer memory. The memory address range may be assigned to a specified performance tier of a plurality of specified performance tiers. A performance value associated with a performance attribute of the memory address range may be ascertained, and based on the ascertained performance value, a weight value may be determined. Based on the ascertained request and the determined weight value, a count value associated with a counter associated with the memory address range may be incremented. Based on an analysis of the count value associated with the counter, a determination may be made as to whether the memory address range is to be assigned to a different specified performance tier of the plurality of specified performance tiers. Based on a determination that the memory address range is to be assigned to the different specified performance tier, the memory address range may be assigned to the specified different performance tier.

Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

Described is a data cache implementing hybrid writebacks and writethroughs. A processing system includes a memory, a memory controller, and a processor. The processor includes a data cache including cache lines, a write buffer, and a store queue. The store queue writes data to a hit cache line and an allocated entry in the write buffer when the hit cache line is initially in at least a shared coherence state, resulting in the hit cache line being in a shared coherence state with data and the allocated entry being in a modified coherence state with data. The write buffer requests and the memory controller upgrades the hit cache line to a modified coherence state with data based on tracked coherence states. The write buffer retires the data upon upgrade. The data cache writebacks the data to memory for a defined event.

Techniques for performing cache operations are provided. The techniques include tracking performance events for a plurality of test sets of a cache, detecting a replacement policy change trigger event associated with a test set of the plurality of test sets, and in response to the replacement policy change trigger event, operating non-test sets of the cache according to a replacement policy associated with the test set.