Aspects of the disclosure provide an interface between a host and a multi-plane flash memory. For example, the interface can include a first storage unit, a second storage unit and a controller. The first storage unit can be configured to receive and store a first plane pipeline command issued from the host, and output the first plane pipeline command to a first plane of the flash memory. The second storage unit can be configured to receive and store a second plane pipeline command issued from the host, and output the second plane pipeline command to a second plane of the flash memory. The controller can be electrically connected to the first storage unit and the second storage unit, and configured to output the first and second plane pipeline commands to the first and second planes, respectively, when no read process is performed on the first plane and the second plane.

A set of memory commands associated with one or more memory dies of a memory device are communicated via a first portion of an interface to the memory device. Communication of a set of data bursts corresponding to the set of memory commands to the one or more memory dies via a second portion of the interface is caused, wherein one or more of the set of memory commands is communicated via the first interface concurrently with one or more of the set of data bursts.

A memory access controlling device and method in a parallel processing system are disclosed. The memory access controlling device includes an optical transceiver configured to receive an optical signal including a memory access frame from an optical circuit switch (OCS), a memory access controller configured to perform a scheduling operation and a memory access control operation based on the memory access frame and transmit a memory processing instruction and memory address information to a memory controller, and the memory controller configured to perform at least one of memory data read or memory data write based on the memory processing instruction and the memory address information. The memory access controller includes a plurality of header processors and is configured to control memory processing instructions to be performed in sequential order based on connection information between each of the header processors and a target memory.

A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device’s primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.

The present disclosure discloses a data processing apparatus, a data processing method, and related products. The data processing apparatus is used as a computing apparatus and is included in a combined processing apparatus. The combined processing apparatus further includes an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus further includes a storage apparatus. The storage apparatus is respectively connected to the computing apparatus and other processing apparatus and is used to store data of the computing apparatus and other processing apparatus. The solution of the present disclosure takes full advantage of parallelism among different storage units to improve utilization of each functional component.

A data pipeline circuit includes an upstream interface circuit that receives sequential data and a downstream interface circuit that transfers the sequential data to a downstream circuit. A ready signal indicates the downstream circuit is ready to receive the sequential data. The data pipeline circuit includes a first data latch, a second data latch and a first status latch. The first data latch receives the sequential data. The first status latch generates an available signal that is asserted to indicate the second data latch is available to receive the sequential data. The second data latch receives the sequential data in response on the available signal being asserted and the ready signal indicating the downstream circuit is not ready to receive the sequential data on the data output. Limiting conditions in which the sequential data is stored in the second data latch significantly reduces power consumption of the data pipeline circuit.

A first command associated with a first memory die is communicated via a first portion of an interface of the memory sub-system. A second command associated with a second memory die is communicated via the first portion of the interface to a second memory die. A data burst corresponding to the first memory die is caused to be communicated via a second portion of the interface, where the second command is communicated via the first portion of the interface concurrently with the data burst communicated via the second portion of the interface.

A set of memory commands associated with one or more memory dies of a memory device are communicated via a first portion of an interface to the memory device. Communication of a set of data bursts corresponding to the set of memory commands to the one or more memory dies via a second portion of the interface is caused, wherein one or more of the set of memory commands is communicated via the first interface concurrently with one or more of the set of data bursts.

An interface circuit of a memory device including a plurality of memory dies including a plurality of registers corresponding to the plurality of memory dies, respectively, the plurality of registers each configured to store command information related to a data operation command, a demultiplexer circuit configured to provide input command information to a selected register from among the plurality of registers according to at least one of a first address or a first chip selection signal, the input command information being received from outside the interface circuit, and a multiplexer circuit configured to receive output command information from the selected register from among the plurality of registers and output the output command information according to at least one of a second address or a second chip selection signal may be provided.