A memory device can include an interface comprising a plurality of control and address connections and at least one set of data connections; memory circuits comprising a plurality of storage locations randomly accessible for read and write operations in response to an address value received on the address connections; and accelerator circuits coupled to the memory circuits and configured to perform at least one predetermined operation on data stored in the memory device to generate modified data for storage within the memory circuits in response to at least one command received on the interface; wherein the at least one command is supplemental to read and write commands executable by the memory device.

In one embodiment, a computer-implemented method includes issuing, to a DRAM with EIP, a first group of two or more load requests to load data from a hash table constructed from hashed join-key values of a dimension table for a hash-join procedure. A second group of two or more load requests is issued. First response data is received, responsive to the first group of load requests. The first response data is processed while awaiting second response data responsive to the second group. Processing the first response data includes identifying matches between the join-key values corresponding to entries in the load requests of the first group and one or more hash buckets in the first response data. The size of the second group of load requests is selected such that a time for processing the first response data is approximately equal to the latency in receiving the second response data.

A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.

Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.

Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.

Techniques are disclosed relating to self-addressing memory. In one embodiment, an apparatus includes a memory and addressing circuitry coupled to or comprised in the memory. In this embodiment, the addressing circuitry is configured to receive memory access requests corresponding to a specified sequence of memory accesses. In this embodiment, the memory access requests do not include address information. In this embodiment, the addressing circuitry is further configured to assign addresses to the memory access requests for the specified sequence of memory accesses. In some embodiments, the apparatus is configured to perform the memory access requests using the assigned addresses.

A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.

An integrated circuit is provided with a memory controller coupled to a buffered command and address bus and a pipelined data bus having a pipeline delay. The memory controller is configured to control the write and read operations for an external memory having a write latency period requirement. The memory controller is further configured to launch write data into the pipelined data bus responsive to the expiration of a modified write latency period that is shorter than the write latency period.

A first command associated with a first memory die is communicated via a first portion of an interface of the memory sub-system. A second command associated with a second memory die is communicated via the first portion of the interface to a second memory die. A data burst corresponding to the first memory die is caused to be communicated via a second portion of the interface, where the second command is communicated via the first portion of the interface concurrently with the data burst communicated via the second portion of the interface.