A system for an artificial neural network (ANN) includes a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell. The main memory may be configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line. The memory controller may be further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.

A network interface device has a data source, a data sink and an interconnect configured to receive data from the data source and to output data to the data sink. The interconnect has a memory having memory cells. Each memory cell has a width which matches a bus segment width. The memory is configured to receive a first write output with a width corresponding to the bus segment width. The write output comprises first data to be written to a first memory cell of the memory, the first data being from the data source.

Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.

A method and a memory device are provided. A controller of the memory device retrieves a first command burst from a host memory. The first command burst includes a sequence of one or more commands from a first submission queue. The controller identifies that at least one command in the first command burst is at least one first fused command of a first set of fused commands. The first set of fused commands is to be processed atomically in the memory device, and a remainder of the first set of fused commands is on the first submission queue. The controller stores at least an identifier of the at least one first fused command in a set-aside buffer of the memory device.

A memory access controlling device and method in a parallel processing system are disclosed. The memory access controlling device includes an optical transceiver configured to receive an optical signal including a memory access frame from an optical circuit switch (OCS), a memory access controller configured to perform a scheduling operation and a memory access control operation based on the memory access frame and transmit a memory processing instruction and memory address information to a memory controller, and the memory controller configured to perform at least one of memory data read or memory data write based on the memory processing instruction and the memory address information. The memory access controller includes a plurality of header processors and is configured to control memory processing instructions to be performed in sequential order based on connection information between each of the header processors and a target memory.

Packet routing between memory devices and related apparatuses, methods, and memory systems are disclosed. An apparatus of a memory device includes a memory controller, two or more memory interfaces, packet relay logic configured to control the two or more memory interfaces, and a switch. The switch is configured to pass a received packet received through a first memory interface of the two or more memory interfaces to the memory controller responsive to a determination that the received packet indicates the memory device as a destination of the received packet. The switch is also configured to pass the received packet through a second memory interface of the two or more memory interfaces toward an other memory device responsive to a determination that the received packet indicates the other memory device as the destination of the received packet.

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

Embodiments of the present invention disclose an information processing method. The method comprises: receiving an acquisition request sent by a terminal for acquiring an image to be displayed, wherein the acquisition request carries an identifier of the image, and the image comprises a first object to be displayed and a second object to be displayed; acquiring, on the basis of the acquisition request, the image corresponding to the identifier, and performing identification on the image to obtain a first image region and a second image region, wherein the first image region comprises the first object, and the second image region comprises the second object; and determining a sending order, and sequentially sending, according to the sending order, the first image region and the second image region to the terminal. Also disclosed by the embodiments of the present invention are a server, a terminal, and a computer storage medium.

A computing system includes a host, a first electronic device connected to the host, and a second electronic device that communicates with the host through the first electronic device. The first electronic device requests a command written in a submission queue of the host based on a doorbell transmitted from the host, stores the command transmitted from the host, requests write data stored in a data buffer of the host, and stores the write data of the data buffer transmitted from the host.

A direct memory access (DMA) circuit is provided. The DMA circuit may include a plurality of groups of direct memory access channels, wherein each of the groups includes at least one DMA channel and a resource usage counter configured to count an execution time in which one of the DMA channels of the group is executed, and an arbiter configured to evaluate a value of the resource usage counter of a group upon a request for execution time by one of the DMA channels of the group, and, taking into account a result of the evaluation, to assign, delay assignment, or deny execution time for using the direct memory access to one of the groups.

Relevant FIG. 2