Embodiments of the present invention disclose an information processing method. The method comprises: receiving an acquisition request sent by a terminal for acquiring an image to be displayed, wherein the acquisition request carries an identifier of the image, and the image comprises a first object to be displayed and a second object to be displayed; acquiring, on the basis of the acquisition request, the image corresponding to the identifier, and performing identification on the image to obtain a first image region and a second image region, wherein the first image region comprises the first object, and the second image region comprises the second object; and determining a sending order, and sequentially sending, according to the sending order, the first image region and the second image region to the terminal. Also disclosed by the embodiments of the present invention are a server, a terminal, and a computer storage medium.

System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

The present disclosure includes an interface for memory having a cache and multiple independent arrays. An embodiment includes a memory device having a cache and a plurality independent memory arrays, a controller, and an interface configured to communicate a plurality of commands from the controller to the memory device, wherein the interface includes a pin configured to activate upon a first one of the plurality of commands being received by the memory device and deactivate once all of the plurality of commands have been executed by the memory device.

A memory system includes a memory circuit including a plurality of pages, including a particular page having a page activation time. The memory system also includes a memory controller circuit configured to receive a memory access request corresponding to data of the particular page. The memory controller circuit is also configured to transmit, in response to a determination that the particular page is inactive, an activation command to the memory circuit to activate the particular page, and to schedule a future transmission of an initial memory command for the particular page based on the page activation time.

A method and a memory device are provided. A controller of the memory device retrieves a first command from a host memory. The controller stores a first identifier of the first command in a set-aside buffer of the memory device. The controller retrieves a second command from the host memory. The controller initiates processing of the first command and the second command based on a second identifier of the second command corresponding to the first identifier

A data transmission system includes a first memory, a second memory, a third memory; and a memory controller. The memory controller includes a first channel control module and a second channel control module. The first channel control module is coupled to the first memory and the second memory. The first channel control module transmits a first set of data between the first memory and the second memory, and transmits a switch signal after the first set of data is transmitted. The second channel control module is coupled to the first channel control module, the first memory, and the third memory. The second channel control module transmits a second set of data between the first memory and the third memory after receiving the switch signal.

Staging buffer arbitration includes: storing a plurality of memory access requests in a staging buffer; selecting a memory access request of the plurality of memory access requests from the staging buffer based on one or more arbitration rules; and moving the memory access request from the staging buffer to a command queue.

A system includes a controller for controlling communication between a first device and a second device connected by way of a communication interface. The controller that is associated with the first device is configured to receive a communication request from a processor of the first device for communicating with the second device. Based on the communication request, the controller is further configured to retrieve a set of instructions from an instruction memory that is associated with the first device. Further, the controller is configured to control the communication interface at each cycle of a clock signal by executing each instruction thus controlling the communication between the first and second devices at each cycle of the clock signal.

A computing system includes a host, a first electronic device connected to the host, and a second electronic device that communicates with the host through the first electronic device. The first electronic device requests a command written in a submission queue of the host based on a doorbell transmitted from the host, stores the command transmitted from the host, requests write data stored in a data buffer of the host, and stores the write data of the data buffer transmitted from the host.

A system includes a controller for controlling communication between a first device and a second device connected by way of a communication interface. The controller that is associated with the first device is configured to receive a communication request from a processor of the first device for communicating with the second device. Based on the communication request, the controller is further configured to retrieve a set of instructions from an instruction memory that is associated with the first device. Further, the controller is configured to control the communication interface at each cycle of a clock signal by executing each instruction thus controlling the communication between the first and second devices at each cycle of the clock signal.