A system includes a memory and a processor in communication with the memory. The processor is configured to execute a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The processor is also configured to output a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Responsive to the validity value being valid, the processor is configured to access the descriptor through the second descriptor address.

A memory controller capable of sequentially increasing or decreasing a total current consumed by a plurality of memory devices, controls a plurality of memory devices coupled through a plurality of channels. The memory controller includes a request checker for identifying memory devices corresponding to requests received from a host among the plurality of memory devices, and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager for outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator for sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse.

A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

A data processor accesses a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent for generating a memory access request, a memory controller for providing a memory command to the memory in response to a normalized request selectively using a first pseudo channel pipeline circuit and a second pseudo channel pipeline circuit, and a data fabric for converting the memory access request into the normalized request selectively for the first pseudo channel and the second pseudo channel.

An apparatus comprises a cache to store information, items of information in the cache being associated with addresses; cache lookup circuitry to perform lookups in the cache; and a prefetcher to prefetch items of information into the cache in advance of an access request being received for said items of information. The prefetcher selects addresses to train the prefetcher. In response to determining that a cache lookup specifying a given address has resulted in a hit and determining that a cache lookup previously performed in response to a prefetch request issued by the prefetcher for the given address resulted in a hit, the prefetcher selects the given address as an address to be used to train the prefetcher.

Disclosed in some examples are methods, systems, and machine readable mediums that provide increased bandwidth caches to process requests more efficiently for more than a single address at a time. This increased bandwidth allows for multiple cache operations to be performed in parallel. In some examples, to achieve this bandwidth increase, multiple copies of the hit logic are used in conjunction with dividing the cache into two or more segments with each segment storing values from different addresses. In some examples, the hit logic may detect hits for each segment. That is, the hit logic does not correspond to a particular cache segment. Each address value may be serviced by any of the plurality of hit logic units.

The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.

Examples described herein relate to an apparatus that includes at least two processing units and a memory hub coupled to the at least two processing units. In some examples, the memory hub includes a home agent. In some examples, the memory hub is to perform a memory access request involving a memory device, a first processing unit among the at least two processing units is to send the memory access request to the memory hub. In some examples, the first processing unit is to offload at least some but not all home agent operations to the home agent of the memory hub. In some examples, the first processing unit comprises a second home agent and wherein the second home agent is to perform the at least some but not all home agent operations before the offload of at least some but not all home agent operations to the home agent of the memory hub. In some examples, based on provision of the at least some but not all home agent operations to be performed by the second home agent, the second home agent is to perform the at least some but not all home agent operations.