A method of a buffer memory device, a storage system, and a buffer memory device are provided. The method of the buffer memory device, the buffer memory device having a lower tier memory and a higher tier memory, may include receiving a new entry request, determining that the new entry request includes an HOL entry, selecting an entry on the higher tier memory to be tiered down to the lower tier memory in response to determining that the new entry request includes an HOL entry, removing the selected entry from the higher tier memory, storing the HOL entry in the higher tier memory of the buffer memory device, and outputting the HOL entry to an arbiter.

The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

In various implementations, provided are systems and methods for an integrated circuit including a completer device, a requester device, and an interconnect fabric. The requester device is configured to generate transactions to the completer device, where each transaction includes a request packet that includes an attribute associated with the completer device; and the interconnect fabric is coupled to the requester device and the completer device. The integrated circuit can also include a QoS regulator configured to identify, based on a first attribute associated with the completer device, a first QoS value establishing a first priority level for a first request packet generated by the requester device, and modify the first request packet to include the first QoS value.

Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.

A memory system includes a memory device including a memory cell array divided into a plurality of memory banks, and a memory controller that sends read requests or write requests to the memory device for the purpose of inputting data to or outputting data from the memory banks of the memory cell array, respectively, and sends the read requests so as to be separated from the write requests based on a read-write switching point. In a first turn, the memory controller sets a near switching point before the read-write switching point. The memory controller blocks scheduling at least one of first bank requests, between the near switching point and the read-write switching point. The memory controller schedules at least one of second bank requests, which cause state switching of the memory banks, so as to be issued between the near switching point and the read-write switching point.

The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.

A memory access device includes: a data processor configured to output an access request requesting access to a memory connected to a data bus, perform a data processing on data in the accessed memory, and provide notification of a progress status of the data processing; a priority switching control part configured to determine an urgency of the data processing by the data processor according to the progress status of the data processing notified from the data processor, and output a priority switching signal notifying switching of a priority of the data processor; and a bus arbiter connected to the data bus, configured to change the priority of the data processor according to the priority switching signal to arbitrate the access request output from the data processor, and control access to the memory according to the access request that has been arbitrated.

Embodiments include herein are directed towards a double data rate (“DDR”) controller system. Embodiments may include a plurality of read data buffers, wherein each of the plurality of read data buffers is configured for read data storage and is of a same size. Embodiments may further include a port read response queue that stores information corresponding to an incoming read and a command queue configured to receive read data buffer state information from the port read response queue. Embodiments may also include a read data buffer allocation tracker configured to track a state of each of the plurality of read data buffers.

A controller for controlling memory devices is provided to include: a first core configured to control first memory devices in communication with the controller and configured to store data associated with first logical addresses; a second core configured to control second memory devices in communication with the controller and configured to store data associated with second logical addresses; and a host interface configured to (1) queue commands received from a host in a queue, (2) perform a command reordering that determines a processing order of queued commands including a first address command associated with a first logical address and a second address command associated with a second logical address based on statuses of the first memory devices and the second memory devices, and (3) provide the first address command to the first core and the second address command to the second core based on the processing order.

A method and a memory device are provided. A controller of the memory device retrieves a first command burst from a host memory. The first command burst includes a sequence of one or more commands from a first submission queue. The controller identifies that at least one command in the first command burst is at least one first fused command of a first set of fused commands. The first set of fused commands is to be processed atomically in the memory device, and a remainder of the first set of fused commands is on the first submission queue. The controller stores at least an identifier of the at least one first fused command in a set-aside buffer of the memory device.