Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

A memory access controlling device and method in a parallel processing system are disclosed. The memory access controlling device includes an optical transceiver configured to receive an optical signal including a memory access frame from an optical circuit switch (OCS), a memory access controller configured to perform a scheduling operation and a memory access control operation based on the memory access frame and transmit a memory processing instruction and memory address information to a memory controller, and the memory controller configured to perform at least one of memory data read or memory data write based on the memory processing instruction and the memory address information. The memory access controller includes a plurality of header processors and is configured to control memory processing instructions to be performed in sequential order based on connection information between each of the header processors and a target memory.

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

A display driver integrated circuit (IC) includes a logic module sequentially issuing read commands including a first read command, a second read command succeeding the first read command, and a third read command succeeding the second read command, and memory modules connected in series with each other. A first memory module is connected to the logic module and is the closest memory module to the logic module. The first memory module receives the read commands, provide the first read command to a first memory of the first memory module, read first image data from the first memory in response to the first read command, and provide the first image data and first remaining read commands among the read commands to a second memory module which is connected to the first memory module and farther than the first memory module from the logic module.

A deaggregated computing system having a memory centric computing storage controller can transfer data from a source to a destination node while dynamically updating a transfer route between them. The transfer route can be recalculated based on the current conditions of the routing nodes between the source and destination. Recalculating the transfer route can be based on power status, bandwidth, in-use status, current capacity, or failure conditions. The deaggregated computing system can include one or more processor units coupled to one or more storage and memory units all connected by the memory centric computing storage controller that can route control and data packets between the processor units and the storage and memory units. The processor units and the storage units can be connected by a combination of serial data communication links and a data storage fabric network.

Packet routing between memory devices and related apparatuses, methods, and memory systems are disclosed. An apparatus of a memory device includes a memory controller, two or more memory interfaces, packet relay logic configured to control the two or more memory interfaces, and a switch. The switch is configured to pass a received packet received through a first memory interface of the two or more memory interfaces to the memory controller responsive to a determination that the received packet indicates the memory device as a destination of the received packet. The switch is also configured to pass the received packet through a second memory interface of the two or more memory interfaces toward an other memory device responsive to a determination that the received packet indicates the other memory device as the destination of the received packet.

Systems, devices, and methods include protective functions in an electrical power system. For example, a processing subsystem may include a first processor and a second processor. The first processor and the second processor may operate independently. A memory subsystem may comprise a first memory section and a second memory section. A memory management subsystem may enable memory access between the first processor and the first memory section and disable memory access between the first processor and the second memory section. The memory management subsystem may further enable memory access between the second processor and the second memory section and disable memory access between the second processor and the first memory section. A protection subsystem may include the first processor and the first memory section and enable a protection function. The second processor and the second memory section may provide a second function that operates independently of the protection function.

Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

An embedded electronic system includes a volatile memory and a processor configured to execute a low-level operating system that manages allocation of areas of the volatile memory to a plurality of high-level operating systems. Each high-level operating system executes one or more of applications. The volatile memory includes a first portion reserved for execution data of a first application and a second portion intended to store execution data of a second application. The system is configured so that once the execution data of the first application are loaded in the first portion, the low-level operating system forbids unloading of the execution data of the first application from the first portion so that the execution data of the first application remain in the volatile memory in case of a deactivation or of a setting to standby of the first application.

A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.