The systems and methods are configured to efficiently and effectively access memory. In one embodiment, a memory controller comprises a request queue, a buffer, a control component, and a data path system. The request queue receives memory access requests. The control component is configured to process information associated with access requests via a first narrow memory channel and a second narrow memory channel. The first narrow memory channel and the second narrow memory channel can have a portion of command/control communication lines and address communication lines that are included in and shared between the first narrow memory channel and the second narrow memory channel. The data path system can include a first data module and one set of unshared data lines associated with the first memory channel and a second data module and another set of unshared data lines associated with second memory channel.

Systems and methods are directed to methods and apparatus for transferring ownership of common resources from a source entity, which owns a resource, to a destination entity, which will own the resource, in a distributed system. The method includes the source entity receiving a command to change ownership (the MOVE command), and then marking the source entity as no longer owning the common resource. The source entity then sends a MOVE command to the destination entity, which will then update its common resource ownership table to reflect that the ownership of the common resource has been transferred from the source entity to the destination entity. It is advantageous that the updating of ownership of the common resource in the source entity occur simultaneously with the dispatching of the MOVE command to the destination entity.

A workgroup-computing-entity-based fail-safe/evolvable hardware core structure is disclosed which includes a 3-hierarchical-level 6-workgroup-Basic-Building-Block (6-wBBB) created to supplant the node-computing-entity-based non-fail-safe/limited evolvable von-Neumann core structure of 3-hierarchical-level 3-node-BBB, (i.e., base-level JO-devices/mid-level main memory/top-level CPU) and all the first-time fail-safe workgroup systems can be subsequently generated in the second period along the workgroup-computing evolutionary timeline. Furthermore, based on the first 6-wBBB evolvable architecture, the workgroup evolutionary processes can go up to 7 generations in creating all the necessary workgroup-computing entity-based hardware core structures, so that all the real-time intelligent workgroup-computing systems can be generated in the third period along the workgroup-computing evolutionary timeline.

The present application discloses a method and a system for transmitting data. A method embodiment comprises: acquiring a most recent shared memory block index of a shared memory segment by a data receiver, the shared memory segment being used by a data transmitter and the data receiver to transmit data; deciding whether the most recent shared memory block index is consistent with a shared memory block index corresponding to data recently read by the data receiver; and determining, according to the decision, whether to read the data in the shared memory block corresponding to the most recent shared memory block index. According to the present application, when the frequency at which the data receiving process processes data is lower than the frequency at which the data transmitting process processes data, the data receiving process directly reads the most recent data and abandons the outdated data which is not processed in time, without influencing other data receiving processes that process data in a higher frequency. Accordingly, the extremely high demand for instantaneity for processing data by a process in the control system of an autonomous vehicle, for example, is satisfied. Therefore, the security and stability of the system are improved.

A method and apparatus of a device that reads and writes a plurality of counters is described. In an exemplary embodiment, a device receives plurality labels that correspond to the plurality of counters. The plurality of counters is stored in a shared memory table in the shared memory of the device. In addition, a writer writes counter data for each of the plurality of counters to the shared memory table. For each of the plurality of labels, the device performs a lookup of that label for a memory reference to a corresponding counter that is one of the plurality of counters and retrieves the memory reference for the corresponding counter. The device further reads the counter data for plurality of counters using the plurality of memory references. The device additionally sends the counter data to the client.

Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

A memory device includes content banks configured to store content data and parity banks configured to store parity data for reconstructing the content data. In response to receiving, in a first clock cycle, a first request requesting a first operation to be performed in a first content bank and a second request requesting to write new content data to the first content bank, the memory device performs the first operation in the first content bank, and writes the new content data to a second content bank. The second content bank is selected from a subset of content banks defined by content banks that correspond with parity banks different from parity banks that correspond with the first content bank. The memory device updates, based on the new content data written to the second content bank, parity data in the parity banks that correspond with the second content bank.

A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.