Examples are disclosed that relate to a multi-port synchronous dynamic random access memory (SDRAM). One example provides a multi-port SDRAM comprising a first port, a second port, a first memory portion, and a second memory portion. At least the first memory portion is configured as shared such that the first memory portion is accessible at the first port and not the second port in a first mode, and the first memory portion is accessible at the second port and not the first port in a second mode. The multi-port SDRAM further comprises a mode controller controllable to selectively change the multi-port SDRAM between at least the first mode and the second mode.

A multi-core processor includes a plurality of cores, a shared memory, a plurality of address allocators, and a bus. The shared memory has a message queue including a plurality of memory regions for transmitting messages between the plurality of cores. The plurality of address allocators are configured to, each time addresses in a predetermined range corresponding to a reference memory region among the plurality of memory regions are received from a corresponding core among the plurality of cores, control the plurality of memory regions to be accessed in sequence by applying an offset determined according to an access count of the reference memory region to the addresses in the predetermined range. The bus is configured to connect the plurality of cores, the shared memory, and the plurality of address allocators to one another.

A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.

According to one embodiment, a method for traffic prioritization in a memory device includes sending a memory access request including a priority value from a processing element in the memory device to a crossbar interconnect in the memory device. The memory access request is routed through the crossbar interconnect to a memory controller in the memory device associated with the memory access request. The memory access request is received at the memory controller. The priority value of the memory access request is compared to priority values of a plurality of memory access requests stored in a queue of the memory controller to determine a highest priority memory access request. A next memory access request is performed by the memory controller based on the highest priority memory access request.

A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.

A packet processing system having each of a plurality of hierarchical clients and a packet memory arbiter serially communicatively coupled together via a plurality of primary interfaces thereby forming a unidirectional client chain. This chain is then able to be utilized by all of the hierarchical clients to write the packet data to or read the packet data from the packet memory.

The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

A computer comprising one or more processors and memory may implement multiple threads that perform a lock operation using a data structure comprising an allocation field and a grant field. Upon entry to a lock operation, a thread allocates a ticket by atomically copying a ticket value contained in the allocation field and incrementing the allocation field. The thread compares the allocated ticket to the grant field. If they are unequal, the thread determines a number of waiting threads. If the number is above the threshold, the thread enters a long term wait operation comprising determining a location for long term wait value and waiting on changes to that value. If the number is below the threshold or the long term wait operation is complete, the thread waits for the grant value to equal the ticket to indicate that the lock is allocated.

A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

In some examples, a system partitions a shared memory address space of a shared memory among a plurality of processing entities into a plurality of memory partitions, where a respective memory partition is associated with a respective processing entity. A first processing entity forwards, to a second processing entity, a first data operation, based on a determination by the first processing entity that the first data operation is to be applied to data for a memory partition associated with the second processing entity. The second processing entity applies the first data operation that includes writing data of the first data operation to the memory partition associated with the second processing entity using a non-atomic operation.