There is provided a data processing apparatus and method. The data processing apparatus comprises a plurality of processing elements connected via a network arranged on a single chip to form a spatial architecture. Each processing element comprising processing circuitry to perform processing operations and memory control circuitry to perform data transfer operations and to issue data transfer requests for requested data to the network. The memory control circuitry is configured to monitor the network to retrieve the requested data from the network. Each processing element is further provided with local storage circuitry comprising a plurality of local storage sectors to store data associated with the processing operations, and auxiliary memory control circuitry to monitor the network to detect stalled data (S60). The auxiliary memory control circuitry is configured to transfer the stalled data from the network to an auxiliary storage buffer (S66) dynamically selected from amongst the plurality of local storage sectors (S64).

Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes and determining a particular endianness format of the plurality of bytes. The method can include, responsive to determining the particular endianness format is a first endianness format, reordering bits of each byte of the plurality of bytes on a bytewise basis, storing the reordered plurality of bytes in an array of memory cells, and adjusting a shift direction associated with performing a number of operations on the plurality of bytes stored in the array. The method can include, responsive to determining the particular endianness format is a second endianness format, storing the plurality of bytes in the array without reordering bits of the plurality of bytes.

Apparatus and methods are disclosed for reordering data received in a non-contiguous order into a contiguous order. In one example of the disclosed technology, an apparatus includes a number of input buffers comprising at least a first, first-in first-out (FIFO) input buffer and a second FIFO input buffer, a number of FIFO output buffers, and a reorder unit configured to store a first portion of non-contiguous data received from an image sensor in the first input buffer, store a second portion of the received data in the second FIFO input buffer, store a respective pixel of data output by the first and second FIFO input buffers at a first address location in the memory, and traverse the memory according to an order to store the respective pixels in a FIFO output buffer. The apparatus can thus be used to reorder pixel data prior to further image processing.

An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.

The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.

An apparatus and a corresponding method for processing a sequence of received data items are disclosed. The processing is performed by multiple processing elements. A reorder buffer comprising multiple slots is used to maintain the order of the received data items, wherein a processing element reserves a next available slot in the reorder buffer before beginning processing the next data item of the sequence of received data items. On completion of the processing a buffer change indicator value is read by the processing element when seeking to insert the processed data item into the reserved slot. If the buffer change indicator changes during the course of the insertion process, this serves as an indication to the processing element that another processing element is modifying the content of the reorder buffer in parallel. A check may be repeated for at least one subsequent already-processed data item, since this latter data item may have become ready to be retired from the reorder buffer.

A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system.

A content data receiving device is provided with a communication interface, a buffer, and a processor. The processor, in a case in which the sequence included in the content data that has been received by the communication interface is discontinuous, performs a retransmission request to a transmission side after causing the buffer to hold the content data, causes the buffer to keep holding the content data that has been received by the communication interface until receiving content data in a continuous sequence, and, in a case of receiving the content data in a continuous sequence, outputs the content data to a subsequent stage so that the sequence is continuous.

A management system (or controller) is configured to send commands to robotic components of different types (e.g., different command types, byte order types, etc.). Once configured, a translation component may be deployed to translate some commands to some robotic components that use a different command type than a native command type used by the management system. The management system uses a native byte order type to create commands, which may be big endian or little endian. While some of the robotic components (e.g., first robotic components) may also use the native byte order type, other robotic components (e.g., second robotic components) may use a non-native byte order type (in relation to the management system). For example, the native byte order type may be big endian while the non-native byte order type may be little endian, or vice versa.

An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.