An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal; generate a second signal based on the transmission data signal, where the second signal has a low slew rate; selectively output the first signal or the second signal as a third signal, in response to a selector signal; and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.

Disclosed embodiments relate, generally, to interfacing serial communication interfaces of a first device with a parallel communication interface of a second device. A first group of two or more serial communication interfaces and an interfacing logic may be provided. The interfacing logic may form second encoded data blocks by arranging the data elements of the first encoded data blocks such that data elements within a same data element position of respective second encoded data blocks represent a given one of the symbols, and provide the second encoded data blocks to a number of serial communication interfaces coupled to a parallel communication interface of another device. An interfacing logic may additionally or alternatively be configured to receive, from a second group of two or more serial communication interfaces, received encoded data blocks representing received symbols.

In at least one embodiment, a method for handling data units in a multi-user system includes granting a shared resource to a user of a plurality of users for a transaction associated with an entry of a transaction data structure. The method includes determining whether the transaction stored last partial data of a data unit associated with the user in an alignment register associated with the user. The method includes asserting a request for arbitration of a plurality of transactions associated with the plurality of users. The request is asserted for an additional transaction associated with the entry in response to determining that the transaction stored the last partial data in the alignment register. The method may include flushing the last partial data from the alignment register to a target memory in response to detecting an additional grant of the shared resource to the user for the additional transaction.

Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.

Resizing circuitry comprises at least one buffer having buffer entries each corresponding to one of at least two shift registers, each shift register comprising storage circuits connected in a ring to transfer a token bit between storage circuits. Selection circuitry controls, based on the shift registers, writing of data sections of input data units having a first number of data sections to the buffer(s), to form output data units having a second number of data sections. For a given buffer entry corresponding to a given shift register, depending on whether the token bit is stored in a first or second subset of storage circuits, the selection circuitry controls writing of a selected data section of a received input data unit to the given buffer entry or prevents overwriting of the given buffer entry. At least two of the shift registers have different relative arrangements of the first and second subsets of storage circuits.

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de)compressed data streams.

A queue manager apparatus converts inbound commands of a first width into scalar format commands to be queued in a command queue. Furthermore, the queue manager converts the scalar format commands residing in the command queue into outbound commands of a second width for transmission. Converting inbound commands to scalar format commands and then converting the scalar format commands to a target width for transmission allows the queue manager to advantageously provide efficient and programmable command transmission between arbitrary processing units, regardless of potentially mismatched native command widths.

The present disclosure relates to an information processing device, a mobile device, and a communication system for enabling further enhancement of safety. When communication is performed with another information processing device to perform high-speed data transmission of transmitting data of a frame including image data, an extended packet including an extended packet header and packet data, and a unique message capable of notifying that at least one of an information processing device, the another information processing device, or the image data is in a state different from a normal time or a usual time are transmitted to the another information processing device or received from the another information processing device, a session key is derived and at least one of generation, verification, or decryption of protection data of the unique message is executed, the image data is stored in the packet data, and the image data and the unique message are transmitted at different timings via a part or whole of a common communication path regarding the communication. The present technology can be applied to, for example, a communication system conforming to an MIPI standard.

Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.

The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.