A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

A data transmission apparatus that transmits transmission data from a first memory to a second memory through a communication channel, the first memory storing data in units of a first data block of a first data size, and the communication channel having a width of a second data size, includes: a storage that stores the transmission data read from the first memory; and a transmission controller that transmits the transmission data stored in the storage from the first memory to the second memory in units of an integral multiple of the second data size, such that data transmission from the first memory to the second memory is efficiently performed.

Data exchanges between an ultra-wide band communication module and a secure element are controlled such that the data exchanges pass through a near-field communication router. The near-field communication router controls routing of the data exchanges so that the data exchanges do not pass through a host circuit that is also coupled to the near-field communication router.

A system, apparatus and method for an interface based system that may be composed of a diverse set of blocks with different data bus sizes. These different data bus sizes can be optimized by permitting partial data transfers on the different sized buses.

A data bit width converter is adapted to: convert first data using a first bit width as a data segment unit and second data using a second bit width as a data segment unit, and provide a cache to temporarily store third data, wherein the first bit width is not equal to the second bit width. The data bit width converter includes a slave, a cache, and a data reconstitution circuit. The slave is configured to read and write the second data. The cache is configured to read and write the third data. The data reconstitution circuit is configured to: convert the first data and the second data, and sequentially search the cache and the slave for the second data according to a searching program, to output the first data, and write the third data to the cache according to a temporary storage program.

A data bit width converter is adapted to: convert first data using a first bit width as a data segment unit and second data using a second bit width as a data segment unit, and provide a cache to temporarily store third data, wherein the first bit width is not equal to the second bit width. The data bit width converter includes a slave, a cache, and a data reconstitution circuit. The slave is configured to read and write the second data. The cache is configured to read and write the third data. The data reconstitution circuit is configured to: convert the first data and the second data, and sequentially search the cache and the slave for the second data according to a searching program, to output the first data, and write the third data to the cache according to a temporary storage program.

The disclosure relates to a memory access unit. One example embodiment is a memory access unit, for providing read-access to read an item from an arbitrary location in a physical memory, independently of addressable locations of the physical memory. The item includes a first number of bits and each addressable location of the physical memory includes a second number of bits. The second number of bits is different from the first number of bits. The memory access unit includes an address input, an address interpreter, an address output, a memory output, a data formatter, and a data output.

A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.

Flow control credit management is provided when converting traffic from a first parallel link width on a first link to a second parallel link width on a second link A current value is calculated for a variable flow control credit exchange rate (R) associated with the first and second links. A first flow control credit indicator is received on the second link, and a credit amount calculated based on the first flow control credit indicator and R. A second flow control credit indicator for the credit amount is then transmitted on the first link.

An apparatus includes a control circuit comprising (i) a first differential data strobe input/output circuit having a first set of driver and termination control inputs and (ii) a second differential data strobe input/output circuit having a second set of driver and termination control inputs. The first and the second sets of driver and termination control inputs are independently programmable. The first and the second differential data strobe input/output circuits operate in a first mode when the first differential data strobe input/output circuit is connected to a first memory device having a first data width and the second differential data strobe input/output circuit is connected to a second memory device having the first data width. The first and the second differential data strobe input/output circuits operate in a second mode when the first differential data strobe input/output circuit and the second differential data strobe input/output circuit are connected in parallel to a single memory device having a second data width.