A PCIe SAS direct link connector includes a cable end and a back board; the cable end fixed on the back board and including a direct link female head, a high-speed line, and a 15 pin plug terminal; the back board including a primary and a secondary cavity position; the direct link female head connected with the high-speed line; the 15 pin plug terminal being an asymmetric bow shape and having a short and a long side, a first contact point disposed on the short side, and a second contact point disposed on the long side; the 15 pin plug terminal connected with the high-speed line; when the 15 pin plug terminal is combined with a server board end connector, the first contact point and the second contact point contact a terminal of the server board end connector, respectively, simplifying the connection structure and improving heat dissipation.

A semiconductor device is configured so that two or more master devices access a slave device via a bus. The semiconductor device includes: a priority generation circuit that generates a priority based on a transfer amount between a specific master device and a specific slave device; and an arbitration circuit that performs an arbitration based on the priority when competition of the accesses occurs.

A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter has a current mode indicating the type of commands currently being transacted, and a cross mode indicating the other type. The arbiter is operable to monitor commands in the command queue for the current mode and the cross mode, and in response to designated conditions, send at least one cross-mode command to the memory interface queue while continuing to operate in the current mode. In response to an end streak condition, the arbiter swaps the current mode and the cross mode, and transacts the cross-mode command.

A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.

A data processing apparatus may include a master device, a slave device, and a controller configured to arbitrate communication between the master device and the slave device by: setting a respective Time-out Counter (TC) for each of requests transmitted from the master device, allocating one or more virtual channels to each of one or more request groups, the one or more virtual channels respectively corresponding to priority levels, associating a request with a virtual channel corresponding to the priority level of the request, for each request group, selecting one of the leading requests of the respective virtual channels according to the TCs and transmitting the selected request to the slave device.

A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

A bus system comprises a master, a first slave, a second slave, and a bus. The master is configured to be able to issue a second request to the second slave after issuing a first request to the first slave and before receiving a response to the first request. The bus comprises: a determination unit configured to, upon receiving the second request, determine whether to permit a transfer of the second request to the second slave; and a suspending unit configured to suspend the transfer of the second request to the second slave while it is determined by the determination unit that the transfer is not permitted. The determination unit determines whether or not the transfer is permitted based on a notification from the first slave regarding processing of the first request.

The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.