A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.

Disclosed are an acceleration control system based on a binarization algorithm, a chip, and a robot, which is configured to read and write an external image memory by means of an AHB bus. The acceleration control system includes a main control module, a binarization module, and a binarization FIFO module, and the main control module is configured to control the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be burst-transmitted to the binarization module for processing when a main state machine is in a burst read mode state, and meanwhile control the binarization FIFO module to read binarized data obtained and when all of the pixel data stored in the image memory is processed, and it is notified to send an interrupt instruction to a CPU.

Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

A method for accessing a data bus includes setting a first-come-first-served basis for determining priorities between masters in addition to a fixed priority being set between the same masters. A number of master ports are connected to a number of masters, and a number of slave ports are connected to a number of slaves. First and second multiplexers are connected between the master ports and the slave ports, a number of decoders are connected to the second multiplexers, and a number of arbiters are connected to the first multiplexers. The master ports have a fixed priority, but each arbiter, in receiving an access-request signal sent by a master port, can determine an order as to which of multiple master ports can access a slave port according to a combination of the fixed priority basis and the first-come-first-served basis. A system and a relevant device are also disclosed.

An EtherCAT master-slave station integrated bridge controller, a control method, a control system and a readable storage medium are provided. Therein, an FPGA-based EtherCAT master-slave station integrated bridge controller is constructed. Because of the hardware parallel computing capability of FPGA, the master station of the EtherCAT master-slave station integrated bridge controller has a hard real-time characteristic so as to ensure real-time sending and receiving of EtherCAT network data and reduce the dependence on CPU performance and operating system real-time performance. The EtherCAT master-slave station integrated bridge controller can serve as a slave device relative to a third-party master station device and meanwhile serve as a master device relative to a third-party slave station device, thus reducing the load of EtherCAT bus network and improving the flexibility of network topology.

Systems, methods, and apparatus for serial bus arbitration are described. A data communication apparatus has a bus interface circuit that uses a line driver to couple the apparatus to a data line of a serial bus. A processor in a slave device is configured to cause the apparatus to assert an in-band interrupt request on a serial bus operated in accordance with an I3C protocol, transmit a slave address of the slave device over a data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted, ignore signaling state of the data line while transmitting the slave address and participate in one or more transactions conducted responsive to assertion of the in-band interrupt request and transmission of the slave address. At least one other slave device transmits an address over the data line during the first bus arbitration transaction.

Disclosed are an acceleration control system based on a binarization algorithm, a chip, and a robot, which is configured to read and write an external image memory by means of an AHB bus. The acceleration control system includes a main control module, a binarization module, and a binarization FIFO module, and the main control module is configured to control the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be burst-transmitted to the binarization module for processing when a main state machine is in a burst read mode state, and meanwhile control the binarization FIFO module to read binarized data obtained and when all of the pixel data stored in the image memory is processed, and it is notified to send an interrupt instruction to a CPU.

An interconnected computer system includes a Peripheral Component Interconnect Express (PCIe) fabric, a first computer system communicatively coupled to the PCIe fabric, a second computer system communicatively coupled to the PCIe fabric, and a shared single-access hardware resource coupled to the PCIe fabric. The first computer system includes a first processor and first memory coupled to the first processor configured to store a first flag indicating a desire of the first computer system to access the shared single-access hardware resource and a turn variable indicating which of the first computer system and the second computer system has access to the shared single-access hardware resource. The second computer system includes a second processor and second memory coupled to the second processor configured to store a second flag indicating a desire of the second computer system to access the shared single-access hardware resource.

Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority of the highest-priority interrupt is higher than the preset priority threshold.