A solid state drive having a drive aggregator and multiple component solid state drives. The drive aggregator associates the host interfaces with different logical address spaces, interprets commands received from the host interfaces in the different logical address spaces, and implements the commands using the plurality of component solid state drives. Some of the host interfaces can be configured to share a common logical address space. Some of the logical address spaces can be configured to have an overlapping region that are hosted on the same set of memory units such that the memory units can be addressed in any of the logical address spaces having the overlapping region.

A data transmission system and an operation method thereof are provided. The data transmission system includes a host, a first device and a second device. The host is configured to set a voltage base of a transmission signal, and configured to pull down or up the transmission signal based on the voltage base of the transmission signal to form a plurality of glitches. The first device is connected to the host to receive the transmission signal. The first device obtains a digital content of the transmission signal according to the glitches, if the voltage base of the transmission signal is set as a first base. The second device is connected to the host to receive the transmission signal. The second device obtains the digital content of the transmission signal according to the glitches, if the voltage base of the transmission signal is set as a second base.

Aspects of the present disclosure relate to an interconnect comprising interfaces to communicate with respective requester and receiver node devices, and home nodes. Each home node is configured to: receive requests from one or more requester nodes, each request comprising a target address corresponding to a target receiver nodes; and transmit each said request to the corresponding target receiver node. Mapping circuitry is configured to: associate each of said plurality of home nodes with a given home node cluster; perform a first hashing of the target address of a given request, to determine a target cluster; perform a second hashing of the target address, to determine a target home node within said target cluster; and direct the given message, to the target home node.

Various data bus monitoring, analysis, and logging systems, devices, and methods are described herein. In one example, an apparatus includes a first circuit configured to monitor first packets among traffic carried by one or more first directional lanes of a communication link established between a host and one or more endpoint devices and determine header information for the first packets. The apparatus includes a second circuit configured to detect second packets among traffic carried by one or more second directional lanes of the communication link based at least in part on the header information determined for the first packets. The apparatus includes an analysis element configured to establish transaction metadata comprising properties of transactions on the communication link based at least on correlations among the first packets and the second packets.

A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

Aspects include obtaining data to be transformed. A selected transformation to be applied to the data is determined based on a storage block address list entry (SBALE) in a storage block address list (SBAL). The SBALE includes at least one field that is used in determining the selected transformation to be applied. The selected transformation is applied on the data to generate transformed data and the transformed data is placed in a location specified by the SBAL.

The present disclosure relates to techniques for facilitating communication and memory transfer between PCIe devices that permit access to an entire address space even though a limited address space is exposed and/or visible via the PCIe BAR registers. To this end, the present disclosure aims to permit memory transfer of large blocks of memory from one device to another including memory invisible to the system (i.e. not exposed via PCIe BAR registers). For example, in some embodiments, a data packet may be received at a port associated with a processor interconnect. The data packet includes a header which contains a first address associated with the port. In response to identifying the first address from the first data packet at the port, the data packet is decoded. During the decoding process, a second address is identified in a payload of the data packet. The second address corresponds to a first memory location, and data associated with the payload of the data packet is then stored to the first memory location.

In a method of scheduling commands for a memory device including a plurality of storage regions, a plurality of host commands used to access the plurality of storage regions are received from a host device. The plurality of host commands are queued in a first command queue. A first scheduling associated with the plurality of host commands is performed based on a mapping table and operation states of the plurality of storage regions. The mapping table includes a correspondence between the plurality of host commands and the plurality of storage regions. The plurality of host commands are executed based on a result of the first scheduling. In response to a bank collision occurring while the plurality of host commands are executed, a second scheduling associated with the plurality of host commands is performed.

A packet header is received from a host and written to a header queue. A direct memory access (DMA) descriptor is received from the host and written to a packet descriptor queue. The DMA descriptor points to packet data in a host memory. The packet data is fetched from host memory and the packet header and the packet data are provided to a network interface.

A communication gateway for communicating data frames for a motor vehicle, the gateway being intended to be connected to a plurality of electronic control units in order to exchange data frames, the gateway including: as many management modules as there are electronic control units; a memory in which are stored a lookup table including an index list, with each of the indices of which is associated a memory space, a level-zero addressing table, a level-one addressing table, a level-two addressing table and an address table of levels; a space manager for managing spaces of the lookup table that is configured to determine a free index in the lookup table, and when a memory space of the lookup table is freed or is filled, to modify the byte stored in each memory region of each addressing table associated with the index.