An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

A method is disclosed for requesting data in a cloud gaming system that includes a cloud storage system and a cloud compute system, each of which has a respective peripheral component interconnect express (PCIe) interface and a respective computer memory. The cloud gaming system includes a PCIe switch connected to both the PCIe interface of the cloud storage system and the PCIe interface of the cloud compute system. The PCIe switch exposes a doorbell register that is monitored by the cloud storage system. The cloud compute system writes to the doorbell register, which causes an interrupt to fire on the cloud storage system. The cloud storage system handles the interrupt, which directs the cloud storage system to read a message from a specified computer memory location. The message directs the cloud storage system to read requested data from a storage device accessible by the cloud storage system.

A system for a multiple chip architecture that enables different system on-chip (SoC) systems with varying compatibilities to interact as one SoC via a transparent interface. The system address maps of the single SoCs are configured so that each provide a system address map of the two SoCs without overlap or address re-mapping when connected to one another via the transparent interface. The transparent interface enables components related to safety/security and interrupt communication of a first and second SoC within the multiple chip system to transparently communicate and interact. The transparent interface can enable sources of both SoCs to be flexibly mapped to interrupt services providers on the first/second SoC within the multiple chip system.

A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

A communications interface for interfacing between a host system and a state machine, the communications interface comprising: an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

A system having a first mode, a second mode and a system bus comprises a peripheral circuit, a power management unit (PMU), an additional wire and a control module. The peripheral circuit has a configuration information representing a circuit state thereof. The power management unit (PMU) generates an interrupt signal. The additional wire transmits therethrough the interrupt signal. The control module, in response to the interrupt signal, stores the configuration information via the system bus when the system is in the first mode and restores the configuration information via the system bus when the system is in the second mode.

A semiconductor apparatus may include a burst operation sensing unit and the interface circuit. The burst operation sensing unit may be configured to generate operation mode conversion signals based on current operation state information and a level variation of at least one signal transmission line. The interface circuit may include one or more analog circuits enabled according to the operation mode conversion signals.

The invention provides a hot plug method and device for a byte-addressable persistent memory, which includes hot-add and hot-remove; wherein the hot-add includes physical add and logical add, and the hot-remove includes logical remove and physical remove; the physical add is used for converting the memory from an uncharged raw media into a manageable block of an operating system; the logical add is used for converting the memory from the manageable block of the operating system into a memory device which capable of mapping a virtual address; the logical remove is used for converting the memory device which capable of mapping the virtual address into the manageable block of the operating system; and the physical remove is used for converting the memory from the manageable block of the operating system into the uncharged raw media. The method and device provided in the invention are suitable for scheduling and deployment the byte addressable persistent memory resource on any computer architecture and have a sound market outlook and application value.

A method and architecture for operating with distributed (or segmented) on-chip digital interfaces such as the Inter-Integrated Circuit protocol and a Serial Peripheral Interface protocol. This method and architecture, illustratively, divides the available address space of the digital interface register arrays of a device into one or more segments referred to as a fundamental digital interface circuit. Such segmentation allows for each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection and for exchanging communication in accordance with a plurality of inputs to the device.