A method includes detecting a micro start of frame packet (μSOF) on a data bus. If there is at least one data packet contained in a microframe during the first threshold period after the μSOF, transmitters are held in an active state. If there is no data packet in the first threshold period after the μSOF, the transmitters are transitioned from the active state to an OFF state. The method also includes transitioning the transmitters from the OFF state to the active state prior to a switchback period before the end of the microframe. The method also includes transitioning the transmitters from the OFF state to the active state if a data packet is received in the OFF state. The method also includes dropping the data packet received in the OFF state and transitioning from the OFF state to the active state when the data packet is dropped.

Techniques disclosed herein relate to dynamically configurable multi-stage pipeline processing units. In one embodiment, a circuit includes a plurality of processing engines and a plurality of switches. Each of the plurality of processing engines includes an input port and an output port. Each of the plurality of switches comprises two input ports and two output ports. For each processing engine, the input port of the processing engine is electrically coupled to one of the switches, the output port of the processing engine is electrically coupled to another one of the switches, and the input port of the processing engine is electrically coupled to the output port of each of the processing engines by the switches.

A bi-directional signal transmission connection cable is disclosed. The bi-directional signal transmission connection cable can be connected between a first and a second electronic device. The bi-directional signal transmission connection cable includes a first connection port, a second connection port, a first repeater chip, a second repeater chip and a plurality of transmission wires. The first and the second repeater chips are symmetrically disposed in the first and the second connection ports. The first repeater chip has a first set of adjustment parameters, and the second repeater chip has a second set of adjustment parameters. Thus, when a signal is transmitted between the first and the second electronic devices via the first connection port, the second connection port, and the plurality of transmission wires, the signal is adjusted by the first set of adjustment parameters and the second set of adjustment parameters.

An information handling system couples a solid state drive assembly having plural solid state drives to a motherboard with a single M.2 connector coupled to the motherboard by interfacing the plural solid state drives with an adapter circuit board having an M.2 interface defined at one end to insert into the motherboard connector and having plural M.2 connectors to interface with the plural solid state drives in a desired configuration, such as a stacked vertical configuration that more efficiently uses motherboard footprint to include persistent memory.

A bi-directional signal transmission connection cable is disclosed. The bi-directional signal transmission connection cable can be connected between a first and a second electronic device. The bi-directional signal transmission connection cable includes a first connection port, a second connection port, a first repeater chip, a second repeater chip and a plurality of transmission wires. The first and the second repeater chips are symmetrically disposed in the first and the second connection ports. The first repeater chip has a first set of adjustment parameters, and the second repeater chip has a second set of adjustment parameters. Thus, when a signal is transmitted between the first and the second electronic devices via the first connection port, the second connection port, and the plurality of transmission wires, the signal is adjusted by the first set of adjustment parameters and the second set of adjustment parameters.

In some embodiments, a system is provided for communicating USB information via an extension medium. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device and the DFP device are communicatively coupled via a non-USB extension medium, and allow a host device communicatively coupled to the UFP device and a USB device communicatively coupled to the DFP device to communicate via USB-compliant techniques. In some embodiments, the DFP device generates synthetic request packets to request additional data packets from the USB device compared to those requested by the host device. In some embodiments, the DFP device is configured to store a request packet in a packet queue if the request packet is received from the UFP device while the DFP device is busy receiving a response to a previous synthetic request packet from the USB device.

A method and apparatus may include receiving data from a first device. The data may be received via a first protocol. The method can also include converting the data to be transmitted via a second protocol. The second protocol may be a high-speed proprietary or standard protocol. The method can also include transmitting the data via the second protocol to a second device.

A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.

A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.

A circuit is disclosed. The circuit includes an input port, an output port, a squelch detector and a disconnect detector. The squelch detector and the disconnect detector are enabled or disabled by a signal such that only one of the squelch detector and the disconnect detector is active at a given time. When the squelch detector is active, a threshold generator generates a squelch threshold for the squelch detector based on a squelch configuration data indicative of a predefined squelch threshold. When the disconnect detector is active, the threshold generator generates a disconnect threshold for the disconnect detector based on a disconnect configuration data indicative of a predefined disconnect threshold.