This document describes systems and techniques that enable independent clocking for configuration and status registers (CSRs). The described systems and techniques can provide a clock signal to a CSR set of an IP block with a derived clock rate an integer division slower than a clock rate of another clock signal that enables operation of the IP block, which may include communication between the IP block and an application processor. The derived clock rate is synchronous to but independent of the clock rate of the clock signal. In this way, the application processor and other entities can access the CSR set independent of clocking of the IP block. For example, the application processor can read from or write to the CSR set without waking the IP block from an Auto Clock Gated mode. By so doing, described aspects of independent clocking can reduce power dissipation associated with the CSR set.

Information is provided to a source device during link training regarding the state of a remote link when an intermediate device using a different protocol is connected between source and sink devices. The intermediate device includes two controllers connected by a cable, the first controller being connected to the source device and the second controller being connected to the sink device. State information regarding the remote device may be provided by a state machine that stores data to a register on the intermediate device. Based on the state of the remote link, the source device is able to generate a representation of the end to end link between the source and sink device, and to perform link training accordingly.

A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request.

Port extension apparatus for providing better usage and utilization efficiency ports of end-user devices are disclosed. Port extension apparatus includes at least a main port module for connection to end-user device, first data port module, data transmission control module, second data port module, and video port module. When a to-be-connected device connects to the first data port module, the first data port module and the main port module form a transmission path enabling data transmission between the to-be-connected device and the end-user device. When the to-be-connected device connects to the second data port module, the data transmission control module controls the data transmission between the to-be-connected device and the end-user device. When the to-be-connected device connects to the video port module, the data transmission control module receives the to-be-displayed information from the end-user device and transmits to the to-be-connected device to display.

To address problems that arise due to differences in bus behavior when running a legacy application on a new device the new device may throttle bus performance in a way that emulates the bus behavior of a legacy device when executing the legacy application.

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

A method and apparatus for timing training on an LVDS interface includes sampling by using the second parallel data as reference data and the first parallel data as scanning data, the first delay stage is obtained; sampling by using the first parallel data as reference data and the second parallel data as scanning data, and setting the initial delay stage of the second parallel data as the first delay stage, the second delay stage is obtained, and setting the sum of the first delay stage and half of the delay stage difference as the delay stage of the first parallel data, then receiving the LVDS differential data. The method is capable of handling the impact of OCV and asymmetry in signal slopes on the effective data window, avoiding glitches, and reducing the requirements for delay chain design.

A sequential asynchronous system and a method for operating the same. The method includes operating a first asynchronous finite state machine at a first clock rate and operating a second asynchronous finite state machine at a second clock rate. The method also includes generating, with fork logic, a fork request based on a first state of the first asynchronous finite state machine and receiving, with join logic, the fork request from the fork logic. The method further includes receiving, with the join logic, a communication request from the second asynchronous finite state machine based on a second state of the second asynchronous finite state machine and initiating, with the join logic, a state transition of the second asynchronous finite state machine. The method also includes providing, with the join logic, a join acknowledgement to the fork logic upon completion of the state transition.

This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.