A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.

A retimer apparatus can include a receiver circuit implemented at least partially in hardware; a configuration register comprising a link management bit set, and one or more bit fields for link management bits indicating link management information; bit stream logic implemented at least partially in hardware to encode an ordered set (OS) with one or more link management bits from the configuration register; and a transmitter circuit implemented at least partially in hardware to transmit OS with the one or more link management bits across a link.

An information handling system may include a motherboard and a floating paddle card. The motherboard may include a host system comprising a host system processor, a logic device configured to perform a functionality of the information handling system in accordance with code stored on non-transitory computer-readable media of the logic device, and a management controller communicatively coupled to the host system processor and the logic device and configured to perform out-of-band management of the information handling system. The floating paddle card may be communicatively coupled to the motherboard and configured to serve as interface between one or more devices coupled to the floating paddle card and the logic device and the management controller, the floating paddle card comprising a microcontroller unit configured to, alone or in combination with other circuitry of the floating paddle card, divide management of the one or more devices between the motherboard and the floating paddle card.

A one-way bus bridge pair that transfers secure data in one direction, the bus bridge pair including a transmitting bus bridge, a receiving bus bridge, and a link. The link can connect the transmitting bus bridge and receiving bus bridge. The transmitting bus bridge may be arranged not to receive any data from the receiving bus bridge, and the receiving bus bridge may be arranged not to send any data to the transmitting bus bridge.

A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

Systems and devices can include a physical layer (PHY) that includes a logical PHY to support multiple interconnect protocols. The logical PHY can include a first set of cyclic redundancy check (CRC) encoders corresponding to a first interconnect protocol, and a second set of CRC encoders corresponding to a second interconnect protocol. A multiplexer can direct data to the first set or the second set of CRC encoders based on a selected interconnect protocol. The logical PHY can include a first set of error correcting code (ECC) encoders corresponding to the first interconnect protocol and a second set of ECC encoders corresponding to the second interconnect protocol. The multiplexer can direct data to the first set or the second set of ECC encoders based on the selected interconnect protocol. In embodiments, different CRC/ECC combinations can be used based on the interconnect protocol and the link operational conditions.

An IIC hang link restoration circuit based on a PCA9511A chip, including: a PCA9511A chip, a negation circuit, and an external MOS tube (Q1). An IC bus inside the PCA9511A chip includes a clock line; the PCA9511A chip has one end connected to a master of the IIC bus and the other end connected to a slave of the IIC bus; the PCA9511A chip is provided with input and output interfaces of the clock line, and a ready signal interface; the negation circuit has one end connected to the ready signal interface and the other end connected to a gate electrode of the external MOS tube (Q1), and a source electrode and a drain electrode of the external MOS tube (Q1) are respectively connected to the input interface and the output interface of the clock line of the PCA9511A chip.

A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

A host-to-host chip includes: first and second ports coupled to first and second hosts respectively; and a host-to-host control circuit coupled to the first port and the second port. When the host-to-host chip is coupled to the second host, the host-to-host control circuit identifies whether the second host is an i-Phone or an Android smartphone. If the host-to-host control circuit identifies that the second host is an i-Phone smartphone, in response to a command from the host-to-host control circuit, the second host switches to host role from device role, and the host-to-host control circuit controls whether data is transmitted between the first host and the second host via a DMA path. If the host-to-host control circuit identifies that the second host is an Android smartphone, the host-to-host control circuit determines that data is transmitted between the first host and the second host in a pass-through mode.

The system on a chip includes at least a first digital domain configured to be reinitialized by a first reinitialization signal, a second digital domain and an interface circuit. The interface circuit includes a starting register in the first digital domain, a destination register in the second digital domain and a synchronization circuit in the first digital domain. The interface circuit is configured to transfer data from the starting register to the destination register upon command of a control signal transmitted by the synchronization circuit. The starting register and the synchronization circuit are configured to not be reinitialized by the first reinitialization signal.