In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

An apparatus may comprise multiplexing circuitry to select an ingress lane from among a plurality of ingress lanes to couple to an egress lane; and retiming circuitry to retime a signal received on the selected ingress lane and transmit the retimed signal on the egress lane.

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Aircraft fly-by-wire systems and related vehicle electrical systems are provided. In one embodiment, an electrical system suitable for use with a control surface of a vehicle, such as an aircraft, is provided. The electrical system includes an asynchronous intermodule bus arrangement, a first vehicle control module, and a second vehicle control module. Each vehicle control module includes a respective interface arrangement to obtain and exchange data from different sensing arrangements with a first frequency, and a respective processing system to obtain the sensed data and determine actuator commands based on the sensed data with a lower frequency.

A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

A subscriber station for a serial bus system are provided. The subscriber station includes a message creating device for creating a message to be transmitted serially via a bus of the bus system for at least one further subscriber station of the bus system, so that the message has a first time segment and a second time segment, and a transceiver device for serially sending the message to the bus in such a way that data in the first time segment are sent with a slower data rate than in the second time segment, the transceiver device having in the second time segment at least at times an exclusive, collision-free access to the bus, the message creating device to insert an identification number into the first time segment and to begin the second time segment at the latest after the final bit of the identification number and an additional bit.