A data transmission system and an operation method thereof are provided. The data transmission system includes a host, a first device and a second device. The host is configured to set a voltage base of a transmission signal, and configured to pull down or up the transmission signal based on the voltage base of the transmission signal to form a plurality of glitches. The first device is connected to the host to receive the transmission signal. The first device obtains a digital content of the transmission signal according to the glitches, if the voltage base of the transmission signal is set as a first base. The second device is connected to the host to receive the transmission signal. The second device obtains the digital content of the transmission signal according to the glitches, if the voltage base of the transmission signal is set as a second base.

A computer system, remote control monitoring system, and remote control monitoring method are provided to instantly provide the local display screen of the local computer to the remote computer for remote real-time display. The remote control monitoring system is arranged in the local computer and has a signal receiver and a remote controller. The signal receiver receives the video signal from the processor, executes the signal transforming process to generate the video signal in different standards. The remote controller executes a network compressing process on the transformed video signal to generate the network transportable video data, and transmits the data to the remote computer for displaying the corresponding remote display screen on the remote computer. The present disclosure enables the implementing of the out-of-band remote displaying.

A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.

Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.

A single wire digital communication system for use with an ultrasonic surgical instrument and an ultrasonic surgical instrument including a single wire digital communication system. The single wire digital communication system includes first transmitter logic buffer and first receiver logic buffer operably coupled to a first single wire device via a first single wire communication bus. The single wire digital communication system also includes a first differential transceiver operational amplifier operably coupled to the first transmitter logic buffer via a first transmitter signal line and operably coupled to the first receiver logic buffer via a first receiver signal line. A second differential transceiver operational amplifier is operably coupled to the first differential transceiver operational amplifier via at least one differential bus. A second single wire device is operably coupled to the differential bus and configured to communicate with the first single wire device.

An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. According to this method, an equalization timeout period used for equalization training can be flexibly configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to better ensure that an equalization parameter is found within the configured equalization timeout period, thereby improving an equalization training success rate.

A data communication apparatus includes a transceiver coupled to a data path and configured to transmit or receive data through the data path; and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether to allow any apparatus to occupy the data path. The interrupt circuit generates an interrupt signal for preventing another apparatus from accessing the data path, in response to an activation signal for transmitting or receiving the data through the transceiver.

An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

A method includes receiving a request for a transfer of data on a bus of a computing device; determining a direction for the transfer, at least in part based on the request; determining a quantity of data for the transfer, at least in part based on the request; determining a power state for a lane of the bus, at least in part based on the direction and the quantity of data for the transfer; and setting the power state for the lane of the bus.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.