The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed.

The invention is directed at a communication device for performing data communication using a human or animal body as transmission medium. The communication device comprises a transceiver unit comprising at least one of a transmitter and a receiver. The communication device also comprises an electrostatic transducer for enabling data communication via a surface of the body with one or more user devices in touch with or located near (i.e. in close proximity, e.g. within a range of 0-10 mm therefrom) the body. The communication device further comprises an ultrasonic transducer for enabling data communication through the body using ultrasonic waves. Both the electrostatic transducer and the ultrasonic transducer are capacitive type transducers connected to and operated via the transceiver unit.

A vendor extension command is used to transport a proprietary message to a device (e.g., a solid state drive), to instruct the device to access and return data stored on the device (e.g., data that can be used for debugging). More specifically, a device that is coupled to a host system by a host bus interface (e.g., a Peripheral Component Interconnect Express bus) receives a command in a vendor extension of a standard driver (e.g., a Non-Volatile Memory Express driver). In response to the command in the vendor extension, data (e.g., debugging data) stored in memory on the device is accessed. The data can then be sent over the host bus interface to the host system. Thus, for example, a proprietary debugging framework can be used with a standards-based device.

Provided is a data bus driving circuit including: a data processing unit that processes input data and outputs processed data; a first logic inversion unit that selects, based on a determination result signal, one of the processed data and inverted data obtained by logically inverting each value of a plurality of bits constituting the processed data, and outputs the selected data to a data bus; and an inversion determination unit that compares the data output from the first logic inversion unit with the input data that has not been processed by the data processing unit, and outputs the determination result signal based on a comparison result.

An on-chip clock controller includes a primary clock gating cell and a secondary clock gating cell. The primary clock gating cell includes a first clock input terminal coupled to receive an input clock signal and a first enable input terminal coupled to receive an enable signal. The primary clock gating cell also include a first clock output terminal configured to generate a first output clock signal based at least in part on the input clock signal and the enable signal. The secondary clock gating includes a second clock input terminal coupled to receive the input clock signal and a second clock output terminal configured to generate a second output clock signal based at least in part on the input clock signal. The enable signal is based at least in part on the second output clock signal.

An I2C apparatus (100) comprising: a master device (102) and two slave devices connected through an I2C bus, whereby the two slave devices are programmed with the same default device address. A first slave device (108) is connected to the bus in a conventional configuration whereas a second slave device (110) is connected to the bus in a cross connected configuration such that a clock pin of the second slave is connected to the serial data line and the data pin of the second slave is connected to the serial clock line. In response to a detection that the data pin of the second slave is connected to the serial clock line, the second slave swaps the lines going from the clock and data pins to processing logic of the second slave; and modifies its default device address to ensure that each slave device has a unique device address.

An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

A semiconductor device (1) according to the present invention includes a plurality of buses (B1 to Bm), a control unit (10) connected to the plurality of buses (B1 to Bm), the control unit (10) being configured to acquire information about a communication specification including information about a drive voltage from each of a plurality of externally-disposed modules (M1 to Mn) through one of the plurality of buses (B1 to Bm), and a switch circuit (13) configured to set a connection between the plurality of modules (M1 to Mn) and the plurality of buses (B1 to Bm) based on the information about the communication specification for each of the plurality of modules (M1 to Mn) acquired by the control unit (10).

The present disclosure is directed to an input/output module. In some embodiments, the input/output module includes: a plurality of communication channels, each channel of the plurality of communication channels configured to connect to one or more field devices; switch fabric configured to selectively facilitate connectivity between an external control module and the one or more field devices via the plurality of communication channels; a serial communications port configured for connecting the input/output module to the control module in parallel with a second input/output module, the serial communications port configured for transmitting information between the input/output module and the control module; and a parallel communications port configured for separately connecting the input/output module to the control module, the parallel communications port configured for transmitting information between the input/output module and the control module, and transmitting information between the input/output module and the second input/output module.