An information handling system receives power from plural power sources by managing bi-directional power transfer at plural cable ports to maintain matched impedance across plural power sources. A power manager of an information handling system exchanges power characteristics with the plural power sources to coordinate power transfer in proportion to current capability of the power sources so that voltage droop at the different external power sources remains the same during variable power draws.

There is disclosed herein a circuitry system comprising first and second IC chips, configured or configurable such that; the first IC chip has an output terminal connected to receive an output signal from an output-signal unit of the first IC chip, the output-signal unit being connected between high and low voltage-reference sources of the first IC chip, the high and low voltage-reference sources being connected to respective high and low voltage-reference terminals of the first IC chip; and the second IC chip has an input terminal connected in a potential-divider arrangement between high and low voltage-reference terminals of the second IC chip, wherein: the high and low voltage-reference terminals of the first IC chip are respectively connected to the high and low voltage-reference terminals of the second IC chip; and the output terminal of the first IC chip is connected to the input terminal of the second IC chip.

A semiconductor chip comprising: an internal clock circuit for generating an internal clock signal; a first phase shift device for shifting the phase of an external clock signal and outputting a phase shifting clock signal; a multiplexer, for selectively outputting one of the internal clock signal and the phase shifting clock signal to be a first clock signal; a second phase shift device, for shifting the phase of the first clock signal and outputting a second clock signal; an first output pad, for outputting the first clock signal; and a controllable pad. The controllable pad is controlled to selectively act as an input pad for receiving the external signal and transmitting the external clock signal to the first phase shift device, or act as a second output pad for transmitting the second clock signal.

Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.

An apparatus comprising a plurality of driver circuits and a plurality of control registers. The plurality of driver circuits may be configured to modify a memory signal that transfers read data across a read line to a memory controller. The plurality of control registers may be configured to enable one or more of the driver circuits. A pull up strength and a pull down strength of the memory signal may be configured in response to how many of the plurality of driver circuits are enabled. The plurality of driver circuits implement an asymmetric pull up and pull down of the memory signal.

Methods, systems, and devices for configurable memory termination are described. In one example, a memory system, such as a memory module or a memory assembly, may include one or more memory devices (e.g., memory arrays, memory chips), and an input/output circuit coupled with the one or more memory devices and for communicating over a channel. The memory system may also include a selection component operable to selectively isolate the input/output circuit from one or more signal paths of the channel based at least in part on receiving a signal from a host device. In some examples, the selection component may be operable to selectively couple the one or more signal paths of the channel with one or more termination resistance elements.

An accessory interface for an electronic host device includes a digital communication bus including a plurality of communication lines configured to pass data between the electronic host device and an electronic accessory device. The accessory interface further includes detection circuitry selectively coupled to the plurality of communication lines via a multiplexer and configured to detect analog voltage levels across the plurality of communication lines, determine a device type of the electronic accessory device based on the detected analog voltage levels, and control the multiplexer to couple the plurality of communication lines to a host processor of the electronic host device upon determining the device type of the electronic accessory device. The host processor is configured to receive the device type of the electronic accessory device and transmit data via the plurality of communication lines to the electronic accessory device in accordance with the device type of the electronic accessory device.

A transceiver is disclosed. The transceiver includes a first receiver line, a first transmitter line, a second receiver line, and a second transmitter line, wherein the first receiver line and the second receiver line are coupled to a receiver line selector and the first transmitter line and the second transmitter line are coupled to a transmitter line selector. A system monitor is included that is configured to monitor a controller area network (CAN) bus and the first transmitter line and to select the second transmitter line and the second receiver line if an error condition is detected through the monitoring of the first transmission line. A bias voltage generator is included to generate a bias voltage for a terminating capacitor of the CAN bus, wherein the bias voltage generator is activated by the system monitor when an error condition is detected in the CAN bus.

A value setting associated with one or more parameters of a host-side interface and a memory-side interface of an input/output (I/O) expander is configured to enable Open NAND Flash Interface (ONFI)-compliant communications between a host system and a target memory die of a memory sub-system. The I/O expander processes one or more ONFI-compliant communications between the host system and the target memory die, wherein the one or more ONFI-compliant communications relate to execution of a memory access operation.

A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.