Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

The invention relates to a bus-capable device having an input interface and an output interface for connecting to a serial bus, particularly a CAN bus, wherein the input interface and the output interface each have at least one signal line connection, and further having a terminating resistor for terminating the bus and a switch apparatus for switching the terminating resistor active as a function of the connection status of the input and output interfaces, wherein the input interface and the output interface each having a supply voltage connection for providing a supply voltage to the output and/or input interfaces of a respective next bus-capable device and a feedback connection for receiving the supply voltage from an output and/or input interface of a respective next bus-capable device, wherein the switch apparatus has an evaluation circuit for determining the presence of the supply voltage at the feedback connections of the input and output interfaces and an activation circuit for switching the terminating resistor active when the supply voltage is found by the evaluation circuit to be absent from the feedback connection of the input interface and/or from the feedback connection of the output interface.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

Systems, methods, and devices can include link layer logic that is to identify, by a link layer device, first data received from the memory in a first protocol format, identify, by the link layer device, second data received from the cache in a second protocol format, multiplex, by the link layer device, a portion of the first data and a portion of the second data to produce multiplexed data; and generate, by the link layer device, a flow control unit (flit) that includes the multiplexed data.

A transceiving circuit includes a first transmitting circuit, a first receiving circuit, a first switching circuit and a processing circuit. The first transmitting circuit includes a first inductor and a second inductor, wherein the second inductor is coupled between a first node and a second node, and an end of the first inductor is coupled to the second node. The first receiving circuit is coupled to a third node. The first switching circuit is configured to conduct or block the first node and the third node. When the transceiving circuit is operated in a transmitting mode, the processing circuit is configured to control the first switching circuit to disconnect the first node with the third node. When the transceiving circuit is operated in a receiving mode, the processing circuit is configured to control the first switching circuit to connect the first node with the third node.

Systems, methods, and apparatuses for offset cancellation are described. A memory device may determine that a channel is in a state that interrupts an active termination of the channel and enable the calibration of a reference voltage (e.g., by the memory device). For example, a channel used for data communications with a second device (e.g., a controller) may initially be in a state of active termination. The memory device may determine that the channel has transitioned to another state that interrupts the active termination. While the channel is in the other state, the memory device may calibrate a reference voltage of a receiver by transmitting calibration signals on the channel and detecting an offset associated with a reference voltage. The memory device may use the detected offset and the reference voltage to identify signals transmitted to the memory device over the channel.

A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

A memory controller is used to access a plurality of NAND flash dies. The memory controller includes an internal memory, an output selection circuit, a control circuit and a data access circuit. The internal memory is configured to store plural sets of access settings corresponding to the NAND flash dies. The output selection circuit is coupled to the internal memory and is configured to select a set of access settings corresponding to a NAND flash die. The control circuit is coupled to the output selection circuit and is configured to generate an output selection signal when accessing the NAND flash die. The data access circuit is coupled to the output selection circuit and is configured to access the NAND flash die according to the set of access settings corresponding thereto.

An interface circuit including: a first transmission circuit outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit outputting a second signal to the transmission line via second transfer pads, the first transmission circuit includes a first termination resistor block including a switch and a first termination resistor connected between the first transfer pads, the second transmission circuit includes a second termination resistor block including a switch and a second termination resistor connected between the second transfer pads, and when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when the first transmission circuit is in a low-power operation mode, the second termination resistor block disconnects the second termination resistor, and when the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block connects the second termination resistor.