A transceiving circuit includes a first transmitting circuit, a first receiving circuit, a first switching circuit and a processing circuit. The first transmitting circuit includes a first inductor and a second inductor, wherein the second inductor is coupled between a first node and a second node, and an end of the first inductor is coupled to the second node. The first receiving circuit is coupled to a third node. The first switching circuit is configured to conduct or block the first node and the third node. When the transceiving circuit is operated in a transmitting mode, the processing circuit is configured to control the first switching circuit to disconnect the first node with the third node. When the transceiving circuit is operated in a receiving mode, the processing circuit is configured to control the first switching circuit to connect the first node with the third node.

A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the k.sup.th module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1).sup.th module clock signal terminal; and a fourth signal line for connecting the (k+1).sup.th module clock signal terminal to a 2k.sup.th module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

In an integrated circuit component having a command interface to receive commands, a data interface to receive write data during a write-data reception interval, and first and second registers, control circuitry within the integrated circuit component responds to one or more of the commands by storing within the first register and the second register, respectively, a first control value that specifies a first termination to be applied to the data interface during the write-data reception interval, and a second control value that specifies a second termination to be applied to the data interface after the write-data reception interval transpires.

A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the k.sup.th module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1).sup.th module clock signal terminal; and a fourth signal line for connecting the (k+1).sup.th module clock signal terminal to a 2k.sup.th module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

An electronic device is disclosed. The electronic device comprises a circuit board, a memory part comprising a plurality of first memory chips mounted on the circuit board, a socket part comprising a plurality of terminals electrically connected to a memory module which comprises a plurality of second memory chips, a memory controller for controlling the operation of the plurality of first memory chips and, when the memory module is connected to the socket part, controlling the operation of the plurality of first memory chips and the plurality of second memory chips, a conductive pattern comprising a control line which sequentially connects, from the memory controller, one or more of the plurality of terminals on the socket part and the plurality of first memory chips, and a capacitive element connected to the control line at a preset position between the one or more terminals on the socket part and the memory controller.

In one embodiment, an apparatus includes: a first controller to couple to an interconnect to which a plurality of devices may be coupled, the first controller to communicate first information via the interconnect according to the native communication protocol; a first transceiver to drive the first information onto a first line of the interconnect; a second transceiver to drive a clock signal onto a second line of the interconnect; and a second controller to communicate second information via the interconnect. In an embodiment, the native communication protocol is a single-ended communication protocol and the second controller is to communicate the second information differentially via the interconnect. Other embodiments are described and claimed.

The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.

Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

A circuit for a bus system is provided. The circuit includes: an ascertainment circuit, which is configured to ascertain a first state in which an absolute difference of a voltage between two bus-side terminals is above a threshold value, to ascertain a second state in which the absolute difference of the voltage between the two bus-side terminals is below a threshold value, to ascertain a bit boundary as a function of a number of state transitions between the first and second state, and a suppression circuit, which is configured to connect a suppression circuit between the two bus-side terminals before the bit boundary.

An interface circuit including: a first transmission circuit outputting a first signal to a transmission line via first transfer pads; and a second transmission circuit outputting a second signal to the transmission line via second transfer pads, the first transmission circuit includes a first termination resistor block including a switch and a first termination resistor connected between the first transfer pads, the second transmission circuit includes a second termination resistor block including a switch and a second termination resistor connected between the second transfer pads, and when the first transmission circuit outputs the first signal, the second termination resistor block detects the first signal, and when the first transmission circuit is in a low-power operation mode, the second termination resistor block disconnects the second termination resistor, and when the first transmission circuit is in a high-speed data transfer mode, the second termination resistor block connects the second termination resistor.