G06F15/17312

Distribution schedule creation method and distribution schedule creation apparatus
10944846 · 2021-03-09 · ·

A method of causing a computer to execute: classifying, based on topology for indicating connection relationships among a data-provision apparatus, distribution-destination apparatuses corresponding to distribution destinations of distribution targets, and relay apparatuses configured to relay communications between the data-provision apparatus and the distribution-destination apparatuses, the mutual distribution-destination apparatuses; identifying a first distribution-destination apparatus having a highest communication speed of a directly connected link among the distribution-destination apparatuses belonging to the group; and creating a distribution schedule of the data in a manner that the data is transmitted from the data-provision apparatus to the first distribution-destination apparatus in the same group, and next, the data is transmitted from the first distribution-destination apparatus to a second distribution-destination apparatus other than the first distribution-destination apparatus in the group.

Memory Network Processor

A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

High performance, scalable multi chip interconnect

A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.

MANAGED SWITCH ARCHITECTURES: SOFTWARE MANAGED SWITCHES, HARDWARE MANAGED SWITCHES, AND HETEROGENEOUS MANAGED SWITCHES
20200396130 · 2020-12-17 · ·

Some embodiments provide a system that includes a set of network controllers for receiving definitions of first and second logical switching elements. The system includes several managed switching elements. The set of network controllers configure the several managed switching elements to implement the defined first and second logical switching elements. The system includes several network hosts that are each (1) communicatively coupled to one of the several managed switching elements and (2) associated with one of the first and second logical switching elements. Network data communicated between network hosts associated with the first logical switching element are isolated from network data communicated between network hosts associated with the second logical switching element.

METHOD FOR DEPLOYING A TASK IN A SUPERCOMPUTER, METHOD FOR IMPLEMENTING A TASK IN A SUPERCOMPUTER, CORRESPONDING COMPUTER PROGRAM AND SUPERCOMPUTER
20200348982 · 2020-11-05 ·

This method for deploying a task involves: allocating nodes (1 . . . 16) to the task; determining, in the network (110), a subnetwork, for interconnecting the allocated nodes, satisfying one or more predefined determination criteria comprising a first criterion according to which the subnetwork uses only links that are not allocated to any other task already deployed or that are allocated to fewer than N other tasks already deployed, N being a predefined number equal to one or more; allocating the subnet, and in particular the links belonging to that subnet, to the task; and implementing inter-node communication routes in the allocated subnet

METHOD FOR IMPLEMENTING A TASK IN A SUPERCOMPUTER, ASSOCIATED COMPUTER PROGRAM AND SUPERCOMPUTER
20200348972 · 2020-11-05 ·

This method for deploying a task comprises: deploying the task in the supercomputer; executing the task; at the end of the execution of the task, detecting at least one link which is not allocated to any task, and setting each detected link in an inactive state, wherein the link requires a power consumption less than the power consumption required by a link associated with at least one task.

METHOD FOR DEPLOYMENT OF A TASK IN A SUPERCOMPUTER, METHOD FOR IMPLEMENTING A TASK IN A SUPERCOMPUTER, CORRESPONDING COMPUTER PROGRAM AND SUPERCOMPUTER
20200348981 · 2020-11-05 ·

This method of deploying a task involves: allocating nodes (1 16) to the task; determining, in the network (110), a subnetwork, for interconnecting the allocated nodes, satisfying one or more predefined determination criteria including a first criterion according to which the determined subnetwork is the one, from among at least two subnetworks meeting the criteria other than the first criterion, using the most switches already allocated, each to at least one already deployed task; allocating the subnetwork, and in particular the links belonging to that subnetwork, to the task; and implementing inter-node communication routes in the allocated subnetwork.

Direction indicator
10817459 · 2020-10-27 · ·

An indication of a direction of transmission over the switching fabric is inserted into a data packet that is transmitted from a tile. The indication of direction may indicate directions from the transmitting tile in which intended recipient tiles are present. The switching fabric prevents (e.g. by blocking the data packet at one of a series of latches) the transmission in a direction not indicated in the data packet. Hence, power saving may be achieved, by preventing the unnecessary transmission of data packets over parts of the switching fabric.

MULTIPLE DIES HARDWARE PROCESSORS AND METHODS

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element

A method of configuring a forwarding element that includes several data plane message processing stages. The method stores a set of action codes in an instruction memory in the data plane of the forwarding element. Each action code identifies an operation to perform on a field of a message received at the data plane. The method determines action codes required to process each field of the message in each message processing stage. The method configures a data-plane processing unit of the forwarding element to concurrently perform a group of the action codes in the same data plane processing stage when (i) the action codes are the same and (ii) operate on the same field of the message.