Patent classifications
G06F15/17312
COMPILER AND HARDWARE INTERACTIONS TO REMOVE ACTION DEPENDENCIES IN THE DATA PLANE OF A NETWORK FORWARDING ELEMENT
A method of configuring a forwarding element that includes several data plane message processing stages. The method stores a set of action codes in an instruction memory in the data plane of the forwarding element. Each action code identifies an operation to perform on a field of a message received at the data plane. The method determines action codes required to process each field of the message in each message processing stage. The method configures a data-plane processing unit of the forwarding element to concurrently perform a group of the action codes in the same data plane processing stage when (i) the action codes are the same and (ii) operate on the same field of the message.
High performance, scalable multi chip interconnect
A flexible, scalable server is described. The server includes plural server nodes each server node including processor cores and switching circuitry configured to couple the processor to a network among the cores with the plurality of cores implementing networking functions within the compute nodes wherein the plurality of cores networking capabilities allow the cores to connect to each other, and to offer a single interface to a network coupled to the server.
Direction indicator
An indication of a direction of transmission over the switching fabric is inserted into a data packet that is transmitted from a tile. The indication of direction may indicate directions from the transmitting tile in which intended recipient tiles are present. The switching fabric prevents (e.g. by blocking the data packet at one of a series of latches) the transmission in a direction not indicated in the data packet. Hence, power saving may be achieved, by preventing the unnecessary transmission of data packets over parts of the switching fabric.
Method and apparatus for routing packet in accelerator network
A method for routing a packet in an accelerator network is provided, the method includes: receiving, by a first accelerator which is any accelerator in an accelerator network, an acceleration request packet which includes an acceleration sequence and to-be-accelerated data from a CPU, the acceleration sequence is used to indicate a plurality of acceleration types used for accelerating the data and indicate an order of the plurality of acceleration types; determining, by the first accelerator, a target loop path of the acceleration request packet based on an acceleration information table which includes location information and acceleration type information of a plurality of accelerators in the accelerator network and accelerators on the target loop path are capable of performing acceleration processing on the acceleration request packet according to an indication of the acceleration sequence; and routing, by the first accelerator, the acceleration request packet according to the target loop path.
Network virtualization apparatus and method
A network control system for managing a plurality of switching elements that implement a plurality of logical datapath sets. The network control system includes first and second controllers for generating requests for modifications to first and second logical datapath sets. The first controller is further for determining whether to make modifications to the first logical datapath set. The second controller is further for determining whether to make modifications to the second logical datapath set. Each controller is further for receiving logical control plane data that specifies logical datapath sets and for converting the logical control plane data to physical control plane data for propagating to the switching elements.
ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD FOR ARITHMETIC PROCESSING DEVICE
An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and are connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and are connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. The arithmetic processing unit includes a pull data turn-back bus that propagates the pull data read from the register file of the home calculator unit to the pull data bus.
SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE
In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced.
The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element
A method of configuring a forwarding element that includes several data plane message processing stages. The method stores a set of action codes in an instruction memory in the data plane of the forwarding element. Each action code identifies an operation to perform on a field of a message received at the data plane. The method determines action codes required to process each field of the message in each message processing stage. The method configures a data-plane processing unit of the forwarding element to concurrently perform a group of the action codes in the same data plane processing stage when (i) the action codes are the same and (ii) operate on the same field of the message.
Switch fabric having a serial communications interface and a parallel communications interface
A switch fabric is disclosed that includes a serial communications interface and a parallel communications interface. The serial communications interface is configured for connecting a plurality of slave devices to a master device in parallel to transmit information between the plurality of slave devices and the master device, and the parallel communications interface is configured for separately connecting the plurality of slave devices to the master device to transmit information between the plurality of slave devices and the master device, and to transmit information between individual ones of the plurality of slave devices. The parallel communications interface may comprise a dedicated parallel communications channel for each one of the plurality of slave devices. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.
Distributed network control system with one master controller per logical datapath set
A method for managing a managed forwarding element (MFE) that forwards data in a network. A network controller publishes, to the MFE, a first set of data for configuring the MFE to perform a set of forwarding operations. The network controller collects, from the MFE, a second set of data regarding current operational state of the MFE. The network controller identifies a difference between a desired operational state of the MFE maintained by the network controller and the collected current operational state of the MFE. Based on the identified difference, the network controller publishes a new third set of data for configuring the MFE to adjust the current operational state of the MFE to the desired state.