The invention discloses connections among dies, in particular to interconnected dies, comprising: protocol conversion circuits, external interconnected interfaces and networks on die. The protocol conversion circuits comprise multiple protocol conversion modules which are used to communicate with various standard mainstream protocol interfaces. The external interconnected interfaces comprise several synchronization controllers which are used to communicate with other interconnected dies. The networks on die comprise transmission buses and routers which are used to transmit data packets from the interfaces or other interconnected dies. At the same time, the synchronization controllers and the protocol conversion modules are respectively connected with boundary nodes of the networks on die. The interconnected dies support interface expansion and inter-chip cascades, hardware circuits are simple and functional levels are clearly divided, with good expandability, which overcomes the defects of closed technology, numerous and jumbled systems and bad expandability of the current multi-die systems.

A device architecture includes a spatially reconfigurable array of processors, such as configurable units of a CGRA, having spare elements, and a parameter store on the device which stores parameters that tag one or more elements as unusable. Technologies are described which change the pattern of placement of configuration data, in dependence on the tagged elements. As a result, a spatially reconfigurable array having unusable elements can be repaired.

A computing system includes an array of configurable units made up of sub-arrays of configurable units. Each sub-array has a first number of configurable compute units and a second number of configurable memory units with a first spatial arrangement. Each configurable unit includes a configuration data store. The system also includes a statically configurable bus system coupled to the configurable units and a tag indicating a sub-array of configurable units having a defect. A defect-aware configuration controller sends configuration data to the configuration data stores to implement a data processing operation using the array of configurable units by generating static route control signals for the statically configurable bus system, based on the tag and without support of a host processor, to send a portion of the configuration data targeted to the sub-array having the defect to a configuration data store of an alternative sub-array of configurable units in the array.

A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.

Hardware accelerators and methods for out-of-order processing are described. In one embodiment, a processor includes a hardware accelerator having a plurality of processing elements coupled to form a plurality of logical rows of a multidimensional processing array and a plurality of logical columns of the multidimensional processing array, wherein a processing element of the plurality of processing elements includes a switch to selectively source, from either of an output for a first dataset from an upstream processing element of the plurality of processing elements or a boundary condition value for a second dataset stored in the processing element, based on a switch control value provided to the processing element; and a core coupled to the hardware accelerator.

The present invention relates to cache coherent node controllers for scale-up shared memory systems. In particular it is disclosed a computer system at least comprising a first group of CPU modules connected to at least one first FPGA Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second FPGA Node Controller connected to a second group of CPU modules running a single instance of an operating system.

Embodiments are provided herein for component composition of a disaggregated computing system. A plurality of general purpose links connecting a computing element to other hardware elements are provided within the disaggregated computing system. Each of the plurality of general purpose links comprise a point-to-point connection to at least one of the other hardware elements such that the plurality of general purpose links conform to a configuration used by the other hardware elements regardless of a type of data being transferred through the plurality of general purpose links.

A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Embodiments relate to a computational device including multiple processor tiles on a die that may have multiple switchable topologies. A topology of the computational device may include one or more virtual circuits. A virtual circuit may include multiple processor tiles. A processor tile of a virtual circuit of a topology may include a configuration vector to control a connection between the processor tile and a neighboring processor tile. A first topology of the computation device may correspond to a first phase of a computation of a program, and a second topology of the computation device may correspond to a second phase of the computation of the program. Other embodiments may be described and/or claimed.