A computer system includes a first group of CPU modules operatively coupled to at least one first Programmable ASIC Node Controller configured to execute transactions directly or through a first interconnect switch to at least one second Programmable ASIC Node Controller connected to a second group of CPU modules running a single instance of an operating system.

A system and method for issuing commands to remote devices comprising determining a criterion that forms a rule for a service, the service comprising a service property, a service method, and a service event, distributing the rule to a behavior engine on a programmable device, the behavior engine comprising a set of rules, and evaluating, at the behavior engine, if a trigger criterion for the rule is met. Upon determining that the trigger criterion is met, the method may further comprise performing an action comprising evaluating, at the behavior engine, if a condition is met, and upon determining that the condition is met, issuing a command to perform a first action comprising setting a service property and calling a service method for all devices including the service property within a scope of the action, defining an action scope.

This application discloses a collective communication method and system, and a computer device. In one example, a collective communication system includes at least a first computing chip and a second computing chip. The first computing chip compresses first data and sends compressed first data to the second computing chip through a communication channel. The second computing chip performs an operation based on the compressed first data.

A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.

A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.

A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

A node controller for a first processor socket group may include a node memory storing a coherence directory and logic. Logic may cause the node controller to: receive a memory operation request directly from a second processor socket group, follow a coherence protocol based on the memory operation request and the coherence directory and directly access a socket group memory of the first processor socket group based on the request.

A switch unit for an Ethernet network having a switch and a microprocessor, the switch including at least three ports, which are connected to inputs and outputs of the switch unit, a signal detector and generator for detecting and initiating a bus activity being arranged in each case between the ports and the inputs and outputs of the switch unit. For each input and output an allocation rule to the other inputs and outputs of the switch unit is stored in a memory, the switch unit being designed such that when a bus activity is detected at a signal detector and generator, the assigned inputs and outputs of this input and output are read out from the memory and the associated signal detectors and generators are woken up so that they generate a bus activity at their inputs and outputs.

Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

The embodiments described herein may improve utilization of an emulator system's resources, and may improve efficiency and effectiveness in bug-identification and/or target-debugging; the components described herein may improve utilization of the emulator's resources, reduce wait time to execute emulation routines, and may limit or eliminate the need to stop or kill emulations in process. The various embodiments described herein allow for dynamically associating domains and targets by dynamically allocating and assigning domains with particular target connections, which are pins and/or wires that connect target pods to the emulation system. An emulation system may comprise one or more target MUXs that are situated between the target connections and the domains, to allow the relationships between target pods and domains to be identified and switched dynamically. The target MUXs may be reprogrammed while emulations are ongoing, in order to redirect data communications between available domains and target pods of target systems.