Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Apparatus adapted for exascale computers are disclosed. The apparatus includes, but is not limited to at least one of: a system, data processor chip (DPC), Landing module (LM), chips including LM, anticipator chips, simultaneous multi-processor (SMP) cores, SMP channel (SMPC) cores, channels, bundles of channels, printed circuit boards (PCB) including bundles, floating point adders, accumulation managers, QUAD Link Anticipating Memory (QUADLAM), communication networks extended by coupling links of QUADLAM, log 2 calculators, exp2 calculators, log ALU, Non-Linear Accelerator (NLA), and stairways. Methods of algorithm and program development, verification and debugging are also disclosed. Collectively, embodiments of these elements disclose a class of supercomputers that obsolete Amdahl's Law, providing cabinets of petaflop performance and systems that may meet or exceed an exaflop of performance for Block LU Decomposition (Linpack).

A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes and a plurality of routers. The routers are operable to route data by selecting from among a plurality of network paths from a target node to a destination node in the dragonfly network based on one or more routing tables.

A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Apparatuses, systems, and techniques to route data transfers between hardware devices. In at least one embodiment, a path over which to transfer data from a first hardware component of a computer system to a second hardware component of a computer system is determined based, at least in part, on one or more characteristics of different paths usable to transfer the data.

A hierarchical array computer architecture comprised of a master computer connected to a plurality of node computers wherein each node has a memory segment. A high speed connection scheme between the master computer and the nodes allows the master computer or individual nodes conditional access to the node memory segments. The resulting architecture creates an array computer with a large distributed memory in which each memory segment of the distributed memory has an associated computing element; the entire array being housed in a blade server type enclosure. The array computer created with this architecture provides a linear increase of processing speed corresponding to the number of nodes.

Methods and apparatus for managing connections between multiple internal integrated circuits (ICs) of, for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter-Chip (HSIC) interface are disclosed. In one exemplary embodiment, a device-initiated and host-initiated connect/disconnect procedure is disclosed, that provides improved timing, synchronization, and power consumption.

A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.